# US 12,603,661 B2 · Analog-to-digital converter, ADC, a method for controlling said ADC, and a method for controlling a digital-analog-converter for said ADC > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,661 B2 - Document ID: US12603661B2 - Status: Granted - Kind: B2 - Application number: 18/527,683 - Filed: 2023-12-04 - Published: 2024-06-20 - Granted: 2026-04-14 - Earliest claimed: 2022-12-20 - Assignees: Stichting IMEC Nederland - Applicants: Stichting IMEC Nederland - Inventors: Stan Van Der Ven; Yao-Hong Liu; Yuming He - Web page: https://patentgrep.com/patent/US12603661B2 ## CPC - H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} - H03M 1/466: {using switched capacitors} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An analog-to-digital converter, ADC, is provided. The ADC comprises a comparator having a first input and a second input. The ADC further comprises a first digital-to-analog converter, DAC, and a second DAC configured to receive a first and a second digital reference signal, respectively. The digital reference signals (Dref) represent a signed binary value. The ADC is configured to compare input voltages (Vin), based on a first sampled input signal of a differential input signal and the first digital reference signal, and based on a second sampled input signal of the differential input signal and the second digital reference signal and, based on said comparison, adjust the reference voltage so as to approximate the differential input signal. ## Claims ### Claim 1 An analog-to-digital converter, ADC, comprising: a comparator having a first input and a second input; a first digital-to-analog converter, DAC, comprising a first capacitor bank having N number of first capacitors, wherein first plates of the first capacitors of the N number of first capacitors are controlled by bits of a first digital reference signal and wherein second plates of the first capacitors of the N number of first capacitors are configured to receive a sampled first input signal of a differential input signal, wherein the first digital reference signal represents a signed binary value, and wherein the first DAC is configured to supply a first input voltage to the first input of the comparator, wherein the first digital reference signal has N+1 number of bits, wherein a most significant bit of the N+1 number of bits is a sign bit, and remaining N bits of the N+1 number of bits are configured to respectively control the N number of first capacitors; and a second DAC, comprising a second capacitor bank having N number of second capacitors, wherein first plates of the second capacitors of the N number of first capacitors are controlled by bits of a second digital reference signal and wherein second plates of the second capacitors of the N number of second capacitors are configured to receive a sampled second input signal of the differential input signal, wherein the second digital reference signal represents a signed binary value, and wherein the second DAC is configured to supply a second input voltage to the second input of the comparator, wherein the second digital reference signal has N+1 number of bits, wherein a most significant bit of the N+1 number of bits is a sign bit, and remaining N bits of the N+1 number of bits are configured to respectively control the N number of second capacitors, wherein the ADC is configured to compare the first and second input voltages and, based on said comparison, adjust the first digital reference signal or the second digital reference signal so as to approximate a difference between the first and second input signals, and wherein the ADC is configured to selectively change the first digital reference signal or the second digital reference signal in dependence of said comparison. ### Claim 2 (depends on 1) The ADC according to claim 1, wherein the signed binary value has N+1 number of bits, wherein the ADC is further configured to selectively change the first digital reference signal or the second digital reference signal in dependence of which of the first input voltage and the second input voltage is larger. ### Claim 3 (depends on 1) The ADC according to claim 1, wherein a first capacitor of each of the first and second capacitor banks is controlled based on a least significant bit, LSB, of the first and second digital reference signal, respectively, and a subsequent capacitor is controlled based on a bit of the first and second digital reference signal, respectively, which is subsequent to the bit for which control of a capacitor which is directly prior to said subsequent capacitor is based on. ### Claim 4 (depends on 3) The ADC according to claim 3, wherein a subsequent capacitor has a capacitance twice that of a capacitor which is directly prior to said subsequent capacitor. ### Claim 5 (depends on 1) The ADC according to claim 1, wherein the ADC (being configured to adjust the first digital reference signal or the second digital reference signal so as to approximate the difference between the first and second input signals comprises: increasing the signed binary value by one least significant bit, LSB, and adjusting the first digital reference signal or the second digital reference signal based on the increased signed binary value. ### Claim 6 (depends on 1) The ADC according to claim 1, wherein the ADC being configured to set the first digital reference signal and the second digital reference signal based on the differential input signal sampled during a first sampling period and compare the differential input signal sampled during a second sampling period to at least one of an upper threshold or a lower threshold for determining whether a level-crossing occurred. ### Claim 7 (depends on 1) The ADC according to claim 1, further comprising circuitry configured to calculate the signed binary value. ### Claim 8 (depends on 1) The ADC according to claim 1, further comprising a sample-and-hold, S&H, circuit configured to provide the input signal to the DAC. ### Claim 9 A method for controlling an analog-to-digital converter, ADC, comprising the steps of: supplying a first digital reference signal to a first capacitor bank of a first digital-to-analog converter, DAC, of the ADC, wherein the first digital reference signal has N+1 number of bits, wherein a most significant bit of the N+1 number of bits is a sign bit, wherein the first capacitor bank has N number of first capacitors and wherein first plates of the first capacitors of N number of first capacitors are controlled by remaining N bits of the N+1 number of bits of the first digital reference signal; supplying a second digital reference signal to a second capacitor bank of a second DAC, wherein the second digital reference signal has N+1 number of bits, wherein a most significant bit of the N+1 number of bits is a sign bit, wherein the second capacitor bank has N number of second capacitors and wherein first plates of the second capacitors of the N number of second capacitors are controlled by remaining N bits of the N+1 number of bits of the second digital reference signal; supplying a sampled first input signal of a differential input signal to second plates of the first capacitors; supplying a sampled second input signal of a differential input signal to second plates of the second capacitors; supplying first and second input voltages to first and second inputs, respectively, of a comparator of the ADC, wherein the first input voltage is based on the first digital reference signal and the sampled first input signal and wherein the second input voltage is based on the second digital reference signal and the sampled second input signal; comparing the first and second input voltages; and adjusting, based on a comparison of the first and second input voltages, the first or second digital reference signal so as to approximate a difference between the first and second input signals, wherein the first and second digital reference signals represent a signed binary value. ### Claim 10 (depends on 9) The method according to claim 9, wherein the signed binary value has N+1 number of bits; and wherein the method further comprises to selectively change the first digital reference signal or the second digital reference signal in dependence of which of the first input voltage and the second input voltage is larger. ### Claim 11 (depends on 9) The method according to claim 9, wherein a first capacitor of each of the first and second capacitor banks is controlled based on a least significant bit, LSB, of the first and second digital reference signal, respectively, and a subsequent capacitor is controlled based on a bit of the first and second digital reference signal, respectively, which is subsequent to the bit for which control of a capacitor which is directly prior to said subsequent capacitor is based on; and wherein a subsequent capacitor has a capacitance twice that of a capacitor which is directly prior to said subsequent capacitor. ### Claim 12 (depends on 9) The method according to claim 9, wherein the step of adjusting the first digital reference signal or the second digital reference signal comprises increasing the signed binary value by one least significant bit, LSB, and adjusting the first digital reference signal or the second digital reference signal based on the increased signed binary value. ### Claim 13 (depends on 9) The method according to claim 9, wherein the step of adjusting the first digital reference signal or the second digital reference signal so as to approximate the difference between the first and second signals utilizes first digital reference signal and second digital reference signal of a previously sampled value, and for a subsequent sample of the differential input signal, the differential input signal may be compared to at least one of an upper threshold or a lower threshold.