# US 12,603,658 B2 · Successive approximation register A/D converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,658 B2 - Document ID: US12603658B2 - Status: Granted - Kind: B2 - Application number: 18/591,467 - Filed: 2024-02-29 - Published: 2024-09-26 - Granted: 2026-04-14 - Earliest claimed: 2021-09-06 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Haruaki Nakamura - Web page: https://patentgrep.com/patent/US12603658B2 ## CPC - H03M 1/1071: {Measuring or testing} - H03M 1/10: Calibration or testing - H03M 1/46: with digital/analogue converter for supplying reference values to converter - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A capacitive array D/A converter samples an input voltage, and outputs a signal that corresponds to the input voltage IN and a threshold voltage based on control data. A comparison circuit receives an output of the capacitive D/A converter and performs comparison processing according to a comparison clock. A clock generating circuit generates a successive approximation clock. A logic circuit supplies the comparison clock to the comparison circuit based on the successive approximation clock. When a predetermined second number of cycles of the successive approximation clock are detected before a predetermined number of cycles of an external clock are detected from the start of A/D conversion, the logic circuit judges that operation is normal. Otherwise, the logic circuit judges that an abnormal state has occurred. ## Claims ### Claim 1 A successive approximation register A/D converter comprising: a capacitive array D/A converter structured to sample an input voltage, to convert control data into a threshold voltage, and to output a signal that corresponds to the input voltage and the threshold voltage; a comparison circuit structured to receive an output of the capacitive array D/A converter, and to perform comparison processing according to a comparison clock; a clock generating circuit structured to generate a successive approximation clock based on an output of the comparison circuit; and a logic circuit structured to receive a comparison signal that indicates a comparison result of the comparison circuit and the successive approximation clock, to update the control data, and to supply the comparison clock based on the successive approximation clock to the comparison circuit, wherein the logic circuit is structured to count the successive approximation clock and an external clock after a start of A/D conversion, to judge that operation is normal when a predetermined second number of cycles of the successive approximation clock is detected before detection of a predetermined first number of cycles of the external clock, and to judge that an abnormal state has occurred when the predetermined second number of cycles of the successive approximation clock have not been detected at a time point at which the first number of cycles of the external clock have been detected, wherein the logic circuit comprises: a first circuit structured to count the external clock after an assertion of a start signal that indicates the start of A/D conversion of the A/D converter, and to assert a first timing signal in response to detection of the first number of cycles of the external clock; a second circuit structured to count the successive approximation clock after the assertion of the start signal and to assert a second timing signal in response to detection of the second number of cycles of the successive approximation clock; and a judgment circuit structured to generate a fail signal that indicates the presence or absence of an abnormal state based on the first timing signal and the second timing signal. ### Claim 2 (depends on 1) The successive approximation register A/D converter according to claim 1, wherein the first circuit comprises a counter structured to operate in synchronization with the external clock and to output a count value of the counter when the second timing signal is asserted. ### Claim 3 (depends on 1) The successive approximation register A/D converter according to claim 1, wherein the second circuit comprises an enable data generating circuit structured to generate enable data having the same number of bits as that of output data of the successive approximation register A/D converter having a bit with a value of “1” that shifts from the most significant bit to the least significant bit for each cycle of the successive approximation clock, and wherein the second circuit is structured to assert the second timing signal when the next successive approximation clock is generated in a state in which the least significant bit of the enable data is “1”. ### Claim 4 A successive approximation register A/D converter comprising: a capacitive array D/A converter structured to sample an input voltage, to convert control data into a threshold voltage, and to output a signal that corresponds to the input voltage and the threshold voltage; a comparison circuit structured to receive an output of the capacitive array D/A converter, and to perform comparison processing according to a comparison clock; a clock generating circuit structured to generate a successive approximation clock based on an output of the comparison circuit; and a logic circuit structured to receive a comparison signal that indicates a comparison result of the comparison circuit and the successive approximation clock, to update the control data, and to supply the comparison clock based on the successive approximation clock to the comparison circuit, wherein the logic circuit is structured to count the successive approximation clock and an external clock after a start of A/D conversion, to judge that operation is normal when a predetermined second number of cycles of the successive approximation clock is detected before detection of a predetermined first number of cycles of the external clock, and to judge that an abnormal state has occurred when the predetermined second number of cycles of the successive approximation clock have not been detected at a time point at which the first number of cycles of the external clock have been detected, wherein the comparison circuit comprises: a first delay circuit structured to delay the comparison clock; and a comparator structured to compare an output of the capacitive array D/A converter according to a latch clock delayed by the first delay circuit. ### Claim 5 (depends on 4) The successive approximation register A/D converter according to claim 4, wherein the first delay circuit is configured as a variable delay circuit. ### Claim 6 (depends on 5) The successive approximation register A/D converter according to claim 5, wherein the first delay circuit provides a delay time that is settable from an exterior. ### Claim 7 (depends on 5) The successive approximation register A/D converter according to claim 5, further comprising a delay time adjustment circuit structured to automatically adjust the delay time of the first delay circuit. ### Claim 8 (depends on 4) The successive approximation register A/D converter according to claim 4, wherein the comparator is structured as a differential comparator having two outputs, wherein, when the latch clock is a first level, the two outputs of the comparator become high, wherein, when the latch clock is a second level, one from among the two outputs of the comparator becomes low according to a comparison result, and wherein the clock generating circuit comprises a NAND gate structured to receive the two outputs of the comparator. ### Claim 9 (depends on 1) The successive approximation register A/D converter according to claim 1, wherein the logic circuit generates a seed pulse in synchronization with the external clock after a start of A/D conversion, and wherein the seed pulse is input to the clock generating circuit. ### Claim 10 (depends on 1) The successive approximation register A/D converter according to claim 1, further comprising a delay circuit structured to delay an output of the clock generating circuit so as to generate the successive approximation clock. ### Claim 11 (depends on 1) The successive approximation register A/D converter according to claim 1, monolithically integrated on a single semiconductor substrate. ### Claim 12 (depends on 4) The successive approximation register A/D converter according to claim 4, wherein the logic circuit generates a seed pulse in synchronization with the external clock after a start of A/D conversion, and wherein the seed pulse is input to the clock generating circuit. ### Claim 13 (depends on 4) The successive approximation register A/D converter according to claim 4, further comprising a second delay circuit structured to delay an output of the clock generating circuit so as to generate the successive approximation clock. ### Claim 14 (depends on 4) The successive approximation register A/D converter according to claim 4, monolithically integrated on a single semiconductor substrate.