Reducing non-linearity in a digital-to-time converter (DTC) due to unequal successive input codes specifying respective delays

A digital-to-time converter (DTC) for generating a fractional output clock from a divided signal based on a sequence of delay-codes, said DTC comprising:

• a delay generator, powered by a power supply, coupled to receive said divided signal and to delay an edge of interest of said divided signal according to each delay-code of said sequence of delay-codes to generate said fractional output clock, wherein the current drawn by said delay generator from said power supply comprises:
• a fixed component having a first current magnitude regardless of magnitude of said corresponding delay-code;
• and
• a variable component having a magnitude determined only by magnitude of corresponding delay-code of said sequence of delay-codes,
• a current-drawing block coupled to draw a correction-current from said power supply, wherein a magnitude of said correction-current is determined only by a complement of the corresponding delay-code of said sequence of delay-codes,
• wherein said current-drawing block operates to ensure that a sum of said correction-current and said variable component drawn by said delay generator is constant regardless of magnitude of said corresponding delay-code,
• wherein total current drawn from said power supply by said delay generator and said current-drawing block equals an aggregate of said sum and said fixed component.

A system comprising:

• a line card coupled to receive a data packet, said line card to re-time said data packet with reference to a selected clock, and to transmit a re-timed packet;
• a first timing card to generate a first clock;
• and
• a power supply,
• wherein said line card comprises:
• a phase-locked loop (PLL) coupled to receive said first clock, said PLL to generate a reference clock locked to said first clock;
• and
• an open-loop-modulator (OLM) coupled to receive said reference clock and to generate a fractional output clock having a frequency which is a desired fraction of that of said reference clock, wherein said OLM comprises:
• a delta-sigma modulator (DSM) coupled to receive said desired fraction and to generate a sequence of first codes and a corresponding sequence of second codes, wherein said sequence of first codes comprises a set of a lower value and a set of a higher value together representing said desired fraction on average;
• a first divider coupled to receive said reference clock and each first code of said sequence of first codes, and to generate a divided signal having a period that is a multiple of the period of said reference clock, wherein the multiple is said each first code;
• a digital-to-time converter (DTC) coupled to generate said fractional output clock from said divided signal, wherein said DTC comprises:
• a delay generator, powered by a power supply, coupled to receive said divided signal and to delay an edge of interest of said divided signal according to corresponding second code of said sequence of second codes to generate said fractional output clock, wherein the current drawn by said delay generator from said power supply comprises:
• a fixed component having a first current magnitude regardless of magnitude of said corresponding second code;
• and
• a variable component having a magnitude determined only by magnitude of corresponding second code of said sequence of second codes,
• a current-drawing block coupled to draw a correction-current from said power supply, wherein a magnitude of said correction-current is determined only by a complement of the corresponding second code of said sequence of second codes,
• wherein said current-drawing block operates to ensure that a sum of said correction-current and said variable component drawn by said delay generator is constant regardless of magnitude of said corresponding second code,
• wherein total current drawn from said power supply by said delay generator and said current-drawing block equals an aggregate of said sum and said fixed component.