Subranging digital to time converter-based fractional phase locked loop architecture

A subranging digital to time converter-based fractional phase locked loop circuit comprising:

• a digital to time converter including a coarse digital to time converter and a fine digital to time converter, wherein the coarse digital to time converter utilizes pseudo-random signal based randomization and the digital to time converter requires no integral non-linearity calibration;
• a phase detector circuit configured to receive a reference frequency and an output of the digital to time converter;
• a phase frequency detector/charge pump circuit configured to receive the reference frequency and the output of the digital to time converter;
• a loop filter and voltage-controlled oscillator (VCO) circuit configured to receive an output of the phase frequency detector/charge pump circuit, wherein the pseudo-random signal based randomization is configured to selectively add a fraction of a VCO period to a first delay associated with the coarse digital to time converter, and to simultaneously subtract the same fraction of the VCO period from a second delay associated with the fine digital to time converter;
• and
• a divider circuit configured to receive an output of the voltage-controlled oscillator circuit and to transmit a signal to the digital to time converter.