# US 12,603,654 B2 · Phase lock loop filter with common mode noise rejection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,654 B2 - Document ID: US12603654B2 - Status: Granted - Kind: B2 - Application number: 18/432,483 - Filed: 2024-02-05 - Published: 2025-08-07 - Granted: 2026-04-14 - Earliest claimed: 2024-02-05 - Assignees: BAE Systems Information and Electronic Systems Integration Inc. - Applicants: BAE Systems Information and Electronic Systems Integration Inc. - Inventors: Norman J. Mendoza - Web page: https://patentgrep.com/patent/US12603654B2 ## CPC - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)} - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A circuit includes (i) an input terminal for receiving a single-ended input signal; (ii) an operational amplifier (op-amp) comprising an inverting input, a non-inverting input, and an op-amp output; (iii) a capacitor coupled between the inverting input and the op-amp output; (iv) a first resistor coupled between the inverting input and the input terminal; and (v) a second resistor coupled between the non-inverting input and the input terminal. In an example, a phase locked loop (PLL) includes the circuit, and a voltage controlled oscillator (VCO) is coupled to the output of the operational amplifier. ## Claims ### Claim 1 A circuit comprising: an input terminal for receiving a single-ended input signal; an operational amplifier (op-amp) comprising an inverting input, a non-inverting input, and an op-amp output; a capacitor coupled between the inverting input and the op-amp output; a first resistor coupled between the inverting input and the input terminal; a second resistor coupled between the non-inverting input and the input terminal; a third resistor coupled in series with the capacitor, and between the inverting input and the op-amp output; wherein a first terminal of the second resistor is coupled to the input terminal and a second terminal of the second resistor is coupled to the non-inverting input, the circuit comprising: a bias voltage supply terminal; and a fourth resistor having first and second terminals, the first terminal of the fourth resistor coupled between the non-inverting input and the second terminal of the second resistor, and the second terminal of the fourth resistor coupled to the bias voltage supply terminal. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the third resistor and the fourth resistor have resistance values that are substantially equal. ### Claim 3 (depends on 1) The circuit of claim 1, wherein the first resistor and the second resistor have resistance values that are substantially equal. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the capacitor is a first capacitor, and wherein the circuit comprises: a second capacitor having (i) a first terminal coupled to the input terminal and (ii) a second terminal coupled to a ground terminal. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the capacitor is a first capacitor, and wherein the circuit comprises: a third resistor having (i) a first terminal coupled to the output of the op-amp and (ii) a second terminal coupled to an output terminal; and a second capacitor having (i) a first terminal coupled to the output terminal and (ii) a second terminal coupled to a ground terminal. ### Claim 6 (depends on 1) The circuit of claim 1, comprising a current source coupled to the input terminal, wherein the current source is configured to generate the single-ended input signal. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the current source is a charge pump generating a charge pump signal that is divided to the inverting input and the non-inverting input. ### Claim 8 (depends on 1) The circuit of claim 1, wherein the single-ended input signal is split at the input terminal to (i) a first signal transmitted through the first resistor, and (ii) a second signal transmitted through the second resistor. ### Claim 9 (depends on 1) A phase locked loop (PLL) comprising: the circuit of claim 1; and a voltage controlled oscillator (VCO) having a voltage control input coupled to the op-amp output. ### Claim 10 (depends on 9) The PLL of claim 9, comprising a phase/frequency detector (PFD) having an output coupled to the input terminal. ### Claim 11 (depends on 10) The PLL of claim 10, wherein the circuit is at least part of a low-pass filter that is coupled between the PFD and the VCO. ### Claim 12 A method comprising: transmitting, by a current source, a single ended current signal; splitting, at an input terminal, the single ended current signal to a first current signal and a second current signal; transmitting the first current signal over a first resistor that is coupled between the input terminal and an inverting terminal of an operational amplifier; transmitting the second current signal over a second resistor that is coupled between the input terminal and a non-inverting terminal of the operational amplifier; generating, at an output terminal coupled to an output of the operation amplifier, an output voltage, the output of the operation amplifier coupled to the inverting terminal of the operational amplifier through a third resistor and a capacitor; and biasing the non-inverting terminal of the operational amplifier through a fourth resistor; wherein the third resistor and the fourth resistor each have a resistance value that are substantially equal, and wherein the first resistor and the second resistor each have a resistance value that are substantially equal. ### Claim 13 (depends on 12) The method of claim 12, further comprising: providing the single ended current signal transmitted by the current source as a pair of differential signals at the operational amplifier.