# US 12,603,652 B1 · Scalable architecture for synchronized arbitrary waveforms > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,652 B1 - Document ID: US12603652B1 - Status: Granted - Kind: B1 - Application number: 18/517,089 - Filed: 2023-11-22 - Granted: 2026-04-14 - Earliest claimed: 2023-11-22 - Assignees: HRL Laboratories, LLC - Applicants: Hrl Laboratories, LLC - Inventors: Randall White; Donald A. Hitko; Daniel S. Matic; Bradley Greene; David Matthews - Web page: https://patentgrep.com/patent/US12603652B1 ## CPC - H03L 7/00: Automatic control of frequency or phase; Synchronisation - H03K 3/01: Details - H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Embodiments relate to a waveform processing device. The device can include a first input node configured to receive a first signal and a second input node configured to receive a second signal. The device can include a pulse generator including a self-timed digital converter (DTC) with a clock generator (CLK). The device can include a switching network configured to be driven by an output from the pulse generator to modulate the first signal and the second signal in synchronization. ## Claims ### Claim 1 A waveform processing device, comprising: a first input node configured to receive a first signal having a first time-varying waveform; a second input node configured to receive a second signal having a second time-varying waveform; a pulse generator including a self-timed digital converter (DTC) with a clock generator (CLK); and a switching network configured to be driven by an output from the pulse generator to modulate the first signal and the second signal in synchronization. ### Claim 2 (depends on 1) The waveform processing device of claim 1, wherein: all components of the device are formed on a single substrate; or at least one component of the device is formed on a first substrate and at least one other component of the device is formed on a second substrate, the first substrate being different from the second substrate. ### Claim 3 (depends on 1) The waveform processing device of claim 1, comprising: plural self-timed DTCs: wherein: each individual self-timed DTC of the plural self-timed DTCs is connected to a single CLK; or more than one self-timed DTC of the plural DTCs is connected to a single CLK. ### Claim 4 (depends on 1) The waveform processing device of claim 1, wherein: the pulse generator is configured to generate a pulse output with a waveform that is one or more of a sine, a triangle, a square, or a sawtooth. ### Claim 5 (depends on 1) The waveform processing device of claim 1, wherein: the self-timed DTC is configured to define a pulse width of a pulse. ### Claim 6 (depends on 1) The waveform processing device of claim 1, wherein: the self-timed DTC is configured to define a pulse repetition interval (PRI) for a pulse. ### Claim 7 (depends on 6) The waveform processing device of claim 6, wherein: the switching network is configured to set an update rate based on the PRI. ### Claim 8 (depends on 7) The waveform processing device of claim 7, wherein: the switching network is configured to set a switching speed based on the PRI. ### Claim 9 (depends on 1) The waveform processing device of claim 1, comprising: plural switching networks, each switching network of the plural switching networks configured to receive an output from the pulse generator and modulate one or more of the first signal or the second signal. ### Claim 10 (depends on 1) The waveform processing device of claim 1, comprising: plural pulse generators; and plural switching networks, an individual switching network of the plural switching networks configured to receive an output from an individual pulse generator of the plural pulse generators and modulate one or more of the first signal or the second signal. ### Claim 11 A waveform processing device, comprising: a first input node configured to receive a first signal, wherein the first input node includes a first digital to analog converter (DAC) configured to generate a voltage V1 based on the first signal; and a second input node configured to receive a second signal, wherein the second input node includes a second DAC configured to generate a voltage V2 based on the second signal; a pulse generator including a self-timed digital time converter (DTC) with a clock generator (CLK) and a reset/set (R/S) latch; and a switching network including a switch driver, a first switch connected to an output of the first DAC, and a second switch connected to an output of the second DAC, wherein the switching network is configured to be driven by an output from the pulse generator to modulate the first signal and the second signal in synchronization. ### Claim 12 (depends on 11) The waveform processing device of claim 11, wherein: the CLK is connected to an input of the self-timed DTC and to a set-input of the R/S latch; and the self-timed DTC is connected to a reset-input of the R/S latch. ### Claim 13 (depends on 11) The waveform processing device of claim 11, wherein: the first DAC is connected to the first switch; the second DAC is connected to the second switch; and the switch driver is connected to the first switch and to the second switch, the switch driver being configured to selectively connect the first DAC and the second DAC to an output node. ### Claim 14 (depends on 13) The waveform processing device of claim 13, comprising: a first buffer connected to the output of the first DAC, wherein an output of the first buffer is connected to the first switch; and a second buffer connected to the output of the second DAC, wherein an output of the second buffer is connected to the second switch. ### Claim 15 (depends on 11) The waveform processing device of claim 11, wherein: the CLK is connected to an input of the self-timed DTC and to a set-input of the R/S latch; the self-timed DTC is connected to a reset-input of the R/S latch; the switch driver is connected to an output of the R/S latch; the first DAC is connected to a first buffer and the first buffer is connected to the first switch; the second DAC is connected to a second buffer and the second buffer is connected to the second switch; and the switch driver is connected to the first switch and to the second switch, the switch driver configured to selectively connect the first buffer and the second buffer to an output node. ### Claim 16 (depends on 11) The waveform processing device of claim 11, comprising: plural switching networks, each switching network of the plural switching networks configured to receive an output from the pulse generator and modulate one or more of the first signal or the second signal. ### Claim 17 (depends on 11) The waveform processing device of claim 11, comprising: plural pulse generators; and plural switching networks, an individual switching network of the plural switching networks configured to receive an output from an individual pulse generator of the plural pulse generators and modulate one or more of the first signal or the second signal. ### Claim 18 A method for synchronizing waveforms, the method comprising: receiving a first signal, having a first time-varying waveform, at a first input node of a waveform processing circuit and a second signal, having a second time-varying waveform, at a second input node of the waveform processing circuit, the waveform processing circuit including: a pulse generator with a self-timed digital time converter (DTC) with a clock generator (CLK); and a switching network connected to the pulse generator; and driving the switching network by an output of the pulse generator to modulate signals received by the waveform processing circuit in synchronization. ### Claim 19 (depends on 18) The method of claim 18, wherein the first input node includes a first digital to analog converter (DAC) configured to generate a voltage V1 based on the first signal, wherein the second input node includes a second DAC configured to generate a voltage V2 based on the second signal, the method comprising: generating a voltage Vout by switching the voltage V1 and the voltage V2 to an output of the switching network to modulate one or more of the first signal and the second signal in synchronization. ### Claim 20 (depends on 18) The method of claim 18, comprising: generating a pulse output from the pulse generator, and defining, via the self-timed DTC, a pulse repetition interval (PRI) for a pulse output generated by the pulse generator.