Electronic device and method that applies stress to transistors

An electronic device comprising:

• a control signal generation circuit configured to generate a stress enable signal to enter a stress process and a measurement enable signal to enter a measurement process based on a voltage control signal and configured to generate a cycle signal enable signal for generating a cycle signal;
• a resistance control circuit configured to generate a resistance control signal based on an external resistance signal;
• and
• a cycle signal generation circuit configured to apply stress to a plurality of transistors when the stress enable signal is activated during the stress process, configured to connect current paths of the plurality of transistors to which the stress is applied when the measurement enable signal is activated during the measurement process, and configured to generate the cycle signal that is cyclically toggled when the cycle signal enable signal is activated;
• wherein a degradation amount of the plurality of transistors attributable to the stress is adjusted based on the resistance control signal.

An electronic device comprising:

• a first internal device configured to generate a reference frequency signal that is cyclically toggled when a cycle signal enable signal is activated;
• a second internal device configured to apply stress to a plurality of transistors by supplying the plurality of transistors with a source voltage and a ground voltage when a stress enable signal is activated during a stress process, configured to connect current paths of the plurality of transistors to which the stress is applied when a measurement enable signal is activated during a measurement process, and configured to generate a cycle signal that is cyclically toggled when the cycle signal enable signal is activated;
• and
• a cycle signal output device configured to latch the cycle signal in synchronization with the reference frequency signal and configured to generate a cycle output signal from the cycle signal that is latched and the reference frequency signal based on a reference selection signal and a subtraction selection signal.

A method comprising:

• during a stress process, blocking current paths of a plurality of transistors and applying stress to the plurality of transistors by supplying the plurality of transistors with a source voltage and a ground voltage;
• and
• during a measurement process, connecting the current paths of the plurality of transistors and applying a cycle signal through the plurality of transistors, and
• wherein the source voltage is generated at a first voltage level during the stress process, the source voltage is generated at a second voltage level during the measurement process, and the first voltage level is higher than the second voltage level.