# US 12,603,647 B2 · Driver circuit of switching transistor, laser driver circuit, and controller circuit of converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,647 B2 - Document ID: US12603647B2 - Status: Granted - Kind: B2 - Application number: 18/442,153 - Filed: 2024-02-15 - Published: 2024-08-22 - Granted: 2026-04-14 - Earliest claimed: 2023-02-22 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Taketo Tsukasa - Web page: https://patentgrep.com/patent/US12603647B2 ## CPC - H03K 17/6872: {using complementary field-effect transistors} - H03K 17/165: {by feedback from the output circuit to the control circuit} - H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load - H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), includes: an output line connected to a gate of the switching transistor; a low-side line connected to a source of the switching transistor; a high-side line; a first PMOS transistor that is connected between the high-side line and the output line; a first NMOS transistor that is connected between the output line and the low-side line; a second PMOS transistor that is connected between the high-side line and the output line; a second NMOS transistor that is connected between the output line and the low-side line; a third NMOS transistor that is connected between the high-side line and the output line; and a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal. ## Claims ### Claim 1 A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), comprising: an output line connected to a gate of the switching transistor; a low-side line connected to a source of the switching transistor; a high-side line; a first PMOS transistor that is connected between the high-side line and the output line and receives a P gate signal at a gate of the first PMOS transistor; a first NMOS transistor that is connected between the output line and the low-side line and receives a first N gate signal at a gate of the first NMOS transistor; a second PMOS transistor that is connected between the high-side line and the output line and receives the first N gate signal at a gate of the second PMOS transistor; a second NMOS transistor that is connected between the output line and the low-side line and receives the P gate signal at a gate of the second NMOS transistor; a third NMOS transistor that is connected between the high-side line and the output line and receives a second N gate signal at a gate of the third NMOS transistor; and a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal, wherein in a turn-on operation of the switching transistor, the first N gate signal transitions to low, subsequently the second N gate signal transitions to high, and subsequently the P gate signal transitions to low more gradually than the transition of the first N gate signal and the transition of the second N gate signal. ### Claim 2 A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), comprising: an output line connected to a gate of the switching transistor; a low-side line connected to a source of the switching transistor; a high-side line; a first PMOS transistor that is connected between the high-side line and the output line and receives a P gate signal at a gate of the first PMOS transistor; a first NMOS transistor that is connected between the output line and the low-side line and receives a first N gate signal at a gate of the first NMOS transistor; a second PMOS transistor that is connected between the high-side line and the output line and receives the first N gate signal at a gate of the second PMOS transistor; a second NMOS transistor that is connected between the output line and the low-side line and receives the P gate signal at a gate of the second NMOS transistor; a third NMOS transistor that is connected between the high-side line and the output line and receives a second N gate signal at a gate of the third NMOS transistor; and a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal, wherein in a turn-off operation of the switching transistor, the P gate signal gradually transitions to high, and subsequently the second N gate signal transitions to low and the first N gate signal gradually transitions to high. ### Claim 3 (depends on 1) The driver circuit of claim 1, further comprising a level shift element connected in series with the third NMOS transistor between the high-side line and the output line. ### Claim 4 (depends on 3) The driver circuit of claim 3, wherein the level shift element includes a diode. ### Claim 5 (depends on 3) The driver circuit of claim 3, wherein the level shift element is a MOS transistor that is capable of being switched in synchronization with the third NMOS transistor. ### Claim 6 (depends on 1) The driver circuit of claim 1, wherein the control circuit includes: a first output inverter whose output is connected to the gate of the first PMOS transistor and the gate of the second NMOS transistor and that outputs the P gate signal; a second output inverter whose output is connected to the gate of the first NMOS transistor and the gate of the second PMOS transistor and that outputs the first N gate signal; and a third output inverter whose output is connected to the gate of the third NMOS transistor and that outputs the second N gate signal, wherein an on-resistance of a PMOS transistor of the second output inverter is larger than an on-resistance of an NMOS transistor of the second output inverter. ### Claim 7 (depends on 6) The driver circuit of claim 6, wherein an on-resistance of an NMOS transistor of the first output inverter is larger than the on-resistance of the NMOS transistor of the second output inverter. ### Claim 8 (depends on 7) The driver circuit of claim 7, wherein an on-resistance of a PMOS transistor of the third output inverter is smaller than the on-resistance of the PMOS transistor of the second output inverter, and an on-resistance of an NMOS transistor of the third output inverter is smaller than the on-resistance of the NMOS transistor of the first output inverter. ### Claim 9 A driver circuit that drives a switching transistor which is a GaN-HEMT (High Electron Mobility Transistor), comprising: an output line connected to a gate of the switching transistor; a low-side line connected to a source of the switching transistor; a high-side line; a first PMOS transistor that is connected between the high-side line and the output line and receives a P gate signal at a gate of the first PMOS transistor; a first NMOS transistor that is connected between the output line and the low-side line and receives a first N gate signal at a gate of the first NMOS transistor; a second PMOS transistor that is connected between the high-side line and the output line and receives the first N gate signal at a gate of the second PMOS transistor; a second NMOS transistor that is connected between the output line and the low-side line and receives the P gate signal at a gate of the second NMOS transistor; a third NMOS transistor that is connected between the high-side line and the output line and receives a second N gate signal at a gate of the third NMOS transistor; and a control circuit that generates the P gate signal, the first N gate signal, and the second N gate signal, wherein in a turn-on operation of the switching transistor, a voltage of the output line rises with a first slope in a first period, rises with a second slope larger than the first slope during a subsequent second period, and rises with a third slope smaller than the second slope during a subsequent third period. ### Claim 10 (depends on 9) The driver circuit of claim 9, wherein a length of the second period is 200 ps to 800 ps. ### Claim 11 (depends on 9) The driver circuit of claim 9, wherein a length of the third period is 1 ns to 5 ns. ### Claim 12 (depends on 1) The driver circuit of claim 1, which is monolithically integrated on one semiconductor substrate. ### Claim 13 (depends on 1) A laser driver circuit comprising a driver circuit of claim 1. ### Claim 14 (depends on 1) A controller circuit of a converter, comprising a driver circuit of claim 1.