# US 12,603,615 B2 · Broadband Doherty power amplifier and implementation method thereof

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- Number: US 12,603,615 B2
- Document ID: US12603615B2
- Status: Granted
- Kind: B2
- Application number: 18/132,426
- Filed: 2023-04-10
- Published: 2023-08-03
- Granted: 2026-04-14
- Earliest claimed: 2021-09-23
- Assignees: Lansus Technologies Inc.
- Applicants: Lansus Technologies Inc.
- Inventors: Liyuan Cai; Kai Xuan; Jiashuai Guo
- Web page: https://patentgrep.com/patent/US12603615B2

## CPC

- H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers}
- H03F 1/42: Modifications of amplifiers to extend the bandwidth
- H03F 1/56: Modifications of input or output impedances, not otherwise provided for
- H03F 3/195: in integrated circuits
- H03F 3/245: {with semiconductor devices only}
- H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
- H03F 2200/36: the amplifier comprising means for increasing the bandwidth
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F: AMPLIFIERS

## Abstract

A broadband Doherty power amplifier is provided, which includes a power divider, a carrier power amplifier circuit, a peak power amplifier circuit, and a load modulation network. The carrier power amplifier circuit includes a carrier input matching circuit, a carrier power amplifier, and a carrier output matching circuit. The peak power amplifier circuit includes a peak input matching circuit, a peak power amplifier and a peak output matching circuit. A resistance value of a system load is ZL. An output impedance of the carrier output matching circuit is Zm and meets Zm=ZL(n+1). An output impedance of the peak output matching circuit is Zp and meets Zp=ZL(n+1)/n. The load modulation network is configured to set an impedance of a combination point to be ZQ, whose resistance value is ZL. A method of implementing a broadband Doherty power amplifier is further provided.

## Claims

### Claim 1

A broadband Doherty power amplifier, comprising:
a power divider;
a carrier power amplifier circuit;
a peak power amplifier circuit; and
a load modulation network;
wherein an input terminal of the power divider serves as an input terminal of the broadband Doherty power amplifier; two output terminals of the power divider are respectively connected to an input terminal of the carrier power amplifier circuit and an input terminal of the peak power amplifier circuit; wherein an output terminal of the carrier power amplifier circuit is connected to a first input terminal of the load modulation network; an output terminal of the peak power amplifier circuit is connected to a second input terminal of the load modulation network; and an output terminal of the load modulation network serves as an output terminal of the broadband Doherty power amplifier, for connecting to a system load;
wherein the carrier power amplifier circuit comprise a carrier input matching circuit, a carrier power amplifier, and a carrier output matching circuit that are sequentially connected in series; wherein an input terminal of the carrier input matching circuit is connected to a first one of the two output terminals of the power divider, and an output terminal of the carrier output matching circuit is connected to the first input terminal of the load modulation network;
wherein the peak power amplifier circuit comprises a peak input matching circuit, a peak power amplifier, and a peak output matching circuit that are sequentially connected in series; wherein an input terminal of the peak input matching circuit is connected to a second one of the two output terminals of the power divider, and an output terminal of the peak output matching circuit is connected to the second input terminal of the load modulation network;
wherein a resistance value of the system load is ZL;
wherein the power divider is configured to respectively allocate power to the carrier power amplifier circuit and the peak power amplifier circuit according to a power division ratio of 1:n;
wherein the carrier input matching circuit is configured to match a terminal impedance of the input terminal of the carrier input matching circuit to an input impedance of the carrier power amplifier, and the carrier output matching circuit is configured to match the resistance value ZL of the system load to an output impedance of the carrier power amplifier; an output impedance of the carrier output matching circuit is Zm, and a following formula is satisfied:
Zm=ZL(n+1); wherein n is a positive number;
wherein the peak input matching circuit is configured to match a terminal impedance of the input terminal of the peak input matching circuit to an input impedance of the peak power amplifier, and the peak output matching circuit is configured to match the resistance value ZL of the system load to an output impedance of the carrier power amplifier; an output impedance of the peak output matching circuit is Zp, and a following formula is satisfied:
Zp=ZL(n+1)/n; and
wherein the load modulation network is configured to perform power combination on an output signal of the carrier output matching circuit and an output signal of the peak input matching circuit, and is configured to set an impedance ZQ of a power amplifier combination point, wherein a resistance value of the impedance ZQ is ZL.

### Claim 2 (depends on 1)

The broadband Doherty power amplifier according to claim 1, wherein the resistance value ZL of the system load is 50 ohms.

### Claim 3 (depends on 2)

The broadband Doherty power amplifier according to claim 2, wherein the power division ratio is 1:1.5, a resistance value of Zm is 125 ohms, a resistance value of Zp is 83.3 ohms, and the resistance value of the impedance ZQ is 50 ohms.

### Claim 4 (depends on 1)

The broadband Doherty power amplifier according to claim 1, wherein the carrier power amplifier circuit is a class AB power amplifier.

### Claim 5 (depends on 4)

The broadband Doherty power amplifier according to claim 4, wherein the carrier power amplifier circuit is implemented by a transistor.

### Claim 6 (depends on 1)

The broadband Doherty power amplifier according to claim 1, wherein the peak power amplifier circuit is a class C power amplifier.

### Claim 7 (depends on 4)

The broadband Doherty power amplifier according to claim 4, wherein the peak power amplifier circuit is implemented by a transistor.

### Claim 8 (depends on 1)

The broadband Doherty power amplifier according to claim 1, wherein the power divider is an in-phase power divider or a phase quadrature power divider.

### Claim 9 (depends on 1)

The broadband Doherty power amplifier according to claim 1, wherein the carrier input matching circuit and the peak input matching circuit each comprises a corresponding phase compensation circuit.

### Claim 10

An implementation method for a broadband Doherty power amplifier, comprising:
S1. implementing a power divider to allocate power to a carrier power amplifier circuit and a peak power amplifier circuit according to a power division ratio of 1:n;
S2. implementing a carrier input matching circuit to match a terminal impedance of an input terminal of the carrier input matching circuit to an input impedance of a carrier power amplifier, and debugging a carrier output matching circuit to match a resistance value of a system load to an output impedance of the carrier power amplifier, where an output impedance of the carrier output matching circuit is Zm, the resistance value of the system load is ZL, and a following formula is satisfied:
Zm=ZL(n+1); wherein n is a positive number;
S3. implementing a peak input matching circuit to match a terminal impedance of an input terminal of the peak input matching circuit to an input impedance of the peak power amplifier, and debugging a peak output matching circuit to match the resistance value ZL of the system load to the output impedance of the carrier power amplifier, where an output impedance of the peak output matching circuit is Zp, and a following formula being satisfied:
Zp=ZL(n+1)/n; and
S4. debugging a load modulation network to perform power combination on an output signal of the carrier output matching circuit and an output signal of the peak input matching circuit, and setting an impedance ZQ of a power amplifier combination point, where a resistance value of the impedance ZQ is ZL;
wherein the broadband Doherty power amplifier comprises:
the power divider;
the carrier power amplifier circuit;
the peak power amplifier circuit; and
the load modulation network;
an input terminal of the power divider serves as an input terminal of the broadband Doherty power amplifier; two output terminals of the power divider are respectively connected to an input terminal of the carrier power amplifier circuit and an input terminal of the peak power amplifier circuit; an output terminal of the carrier power amplifier circuit is connected to a first input terminal of the load modulation network; an output terminal of the peak power amplifier circuit is connected to a second input terminal of the load modulation network; and an output terminal of the load modulation network serves as an output terminal of the broadband Doherty power amplifier for connecting to a system load;
wherein the carrier power amplifier circuit comprises the carrier input matching circuit, the carrier power amplifier, and the carrier output matching circuit sequentially connected in series; the input terminal of the carrier input matching circuit is connected to a first one of the two output terminals of the power divider, and an output terminal of the carrier output matching circuit is connected to the first input terminal of the load modulation network; and
wherein the peak power amplifier circuit comprises the peak input matching circuit, the peak power amplifier, and the peak output matching circuit sequentially connected in series; the input terminal of the peak input matching circuit is connected to a second one of the two output terminals of the power divider, and an output terminal of the peak output matching circuit is connected to the second input terminal of the load modulation network.