US 12,603,611 B2 · Radio frequency (RF) circuit including mixer configured for independent second order intercept point (IP2) calibration

Abstract

A radio frequency (RF) circuit and associated method include a mixer configured for independent second order intercept point (IP2) calibration. The mixer includes three ports and multiple dual-gate transistors interconnected therebetween for down-converting an RF input signal to a lower frequency baseband output signal. To optimize performance, front gates of the transistors are biased with a front gate bias voltage (Vfg). To adjust second order non-linearity, back gates of the transistors are biased using a first back gate bias voltage (Vbgp) for half of the transistors of the mixer and a second back gate bias voltage (Vbgm) for a different half of the transistors. The circuit can also include a front gate bias voltage generator for generating Vfg and a back gate bias voltage generator (including a digital-to-analog converter (DAC) with multiple DAC units) for generating Vbgp and Vbgm independent of Vfg.

Claims16

Dependent claims

A circuit comprising:

a mixer including:
a first transistor connected between a first input node and an output node;
a second transistor connected between an additional first input node and the output node;
a third transistor connected between the first input node and an additional output node;
and a fourth transistor connected between the additional first input node and the additional output node,
wherein a first front gate of the first transistor, a second front gate of the second transistor, a third front gate of the third transistor, and a fourth front gate of the fourth transistor are connected to receive a front gate bias voltage,
wherein a first back gate of the first transistor and a second back gate of the second transistor are connected to receive a first back gate bias voltage, and
wherein a third back gate of the third transistor and a fourth back gate of the fourth transistor are connected to receive a second back gate bias voltage different from the first back gate bias voltage.

5 more elements

A circuit comprising:

a front gate bias voltage generator outputting a front gate bias voltage;
a back gate bias voltage generator outputting a first back gate bias voltage and a second back gate bias voltage;
and
a mixer including:
a first transistor connected between a first input node and an output node;
a second transistor connected between an additional first input node and the output node;
a third transistor connected between the first input node and an additional output node;
and a fourth transistor connected between the additional first input node and the additional output node,
wherein a first front gate of the first transistor, a second front gate of the second transistor, a third front gate of the third transistor, and a fourth front gate of the fourth transistor are connected to receive the front gate bias voltage,
wherein a first back gate of the first transistor and a second back gate of the second transistor are connected to receive the first back gate bias voltage,
wherein a third back gate of the third transistor and a fourth back gate of the fourth transistor are connected to receive the second back gate bias voltage, and
wherein the first back gate bias voltage and the second back gate bias voltage are different and programmed to adjust second order non-linearity of the mixer.

9 more elements

Dependencies are inferred from the claim text.

Radio frequency (RF) circuit including mixer configured for independent second order intercept point (IP2) calibration

Life of this patent

Radio frequency (RF) circuit including mixer configured for independent second order intercept point (IP2) calibration

Life of this patent

Abstract

Claims16