# US 12,603,572 B2 · Conduction mode (CRM) control in digital power supply using mosfet drain-to-source edge detection

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- Number: US 12,603,572 B2
- Document ID: US12603572B2
- Status: Granted
- Kind: B2
- Application number: 18/608,044
- Filed: 2024-03-18
- Published: 2025-09-18
- Granted: 2026-04-14
- Earliest claimed: 2024-03-18
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Xun Gong; Bin Huang
- Web page: https://patentgrep.com/patent/US12603572B2

## CPC

- H02M 3/157: with digital control
- H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)}
- H02M 1/0009: {Devices or circuits for detecting current in a converter}
- H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter}
- H02M 1/38: Means for preventing simultaneous conduction of switches
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A method of operating a DC-DC converter includes generating a high-side control signal for a high-side transistor and generating a low-side control signal for a low-side transistor to thereby cause conversion of an input voltage to an output voltage. A time shift is measured between a falling edge of the low-side control signal and a time at which a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage. A time shift error is determined as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal. A frequency of the high-side control signal and the low-side control signal is adjusted, based upon the time shift error, to maintain the DC-DC converter as operating in critical conduction mode.

## Claims

### Claim 1

A method of operating a DC-DC converter, comprising:
generating a high-side control signal for a high-side transistor of the DC-DC converter and generating a low-side control signal for a low-side transistor of the DC-DC converter to thereby cause conversion of an input voltage to an output voltage;
measuring a time shift between a falling edge of the low-side control signal and a time at which a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage;
determining a time shift error as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal; and
adjusting a frequency of the high-side control signal and the low-side control signal, based upon the time shift error, to maintain the DC-DC converter as operating in critical conduction mode.

### Claim 2 (depends on 1)

The method of claim 1, wherein adjusting the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, is performed by:
decreasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is greater than the dead time.

### Claim 3 (depends on 2)

The method of claim 2, further comprising maintaining the DC-DC converter as operating in the critical conduction mode, or switching operation of the DC-DC converter to the critical conduction mode, based upon the measured time shift being greater than the dead time.

### Claim 4 (depends on 2)

The method of claim 2, wherein adjusting the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, is performed by:
increasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is less than the dead time.

### Claim 5 (depends on 4)

The method of claim 4, further comprising maintaining the DC-DC converter as operating in the critical conduction mode based upon the measured time shift being less than the dead time.

### Claim 6 (depends on 1)

The method of claim 1, further comprising changing the set threshold voltage to thereby change a level of negativity of the inductor current occurring during the dead time.

### Claim 7 (depends on 1)

The method of claim 1, further comprising increasing the set threshold voltage to increase a level of negativity of the inductor current occurring during the dead time.

### Claim 8 (depends on 1)

The method of claim 1, further comprising decreasing the set threshold voltage to decrease a level of negativity of the inductor current occurring during the dead time.

### Claim 9

A power converter, comprising:
a DC-DC converter including a high-side transistor and a low-side transistor, the DC-DC converter being operable to convert an input voltage to an output voltage;
pulse width modulation (PWM) circuitry configured to generate a high-side control signal for the high-side transistor and generate a low-side control signal for the low-side transistor to thereby cause conversion of the input voltage to the output voltage;
a comparator configured to assert its output in response to a drain-to-source voltage of the low-side transistor being greater than a set threshold voltage;
time-shift capture circuitry configured to measure a time shift between a falling edge of the low-side control signal and a time at which the comparator is asserted;
time-shift control circuitry configured to determine a time shift error as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal;
frequency adjustment circuitry configured to generate an output signal indicative of a frequency of the high-side control signal and the low-side control signal, based upon the time shift error, that would maintain the DC-DC converter as operating in critical conduction mode; and
a policy circuit configured to generate a PWM control signal for the PWM circuitry, based upon the output signal from the frequency adjustment circuitry;
wherein the PWM circuitry operates based upon the PWM control signal.

### Claim 10 (depends on 9)

The power converter of claim 9, further comprising a coupling clamp configured to clamp the drain-to-source voltage of the low-side transistor and provide that clamped drain-to-source voltage to the comparator.

### Claim 11 (depends on 10)

The power converter of claim 10, further comprising a digital-to-analog converter configured to generate the set threshold voltage.

### Claim 12 (depends on 9)

The power converter of claim 9, wherein the frequency adjustment circuitry adjusts the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, by decreasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is greater than the dead time.

### Claim 13 (depends on 12)

The power converter of claim 12, wherein the policy circuitry is further configured to maintain the DC-DC converter as operating in the critical conduction mode, or switch operation of the DC-DC converter to the critical conduction mode, based upon the measured time shift being greater than the dead time.

### Claim 14 (depends on 12)

The power converter of claim 12, wherein the frequency adjustment circuitry adjusts the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, by increasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is less than the dead time.

### Claim 15 (depends on 14)

The power converter of claim 14, wherein the policy circuitry is further configured to maintain the DC-DC converter as operating in the critical conduction mode based upon the measured time shift being less than the dead time.