# US 12,603,228 B2 · Multilayer ceramic capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,228 B2 - Document ID: US12603228B2 - Status: Granted - Kind: B2 - Application number: 18/619,252 - Filed: 2024-03-28 - Published: 2025-09-18 - Granted: 2026-04-14 - Earliest claimed: 2024-03-13 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Kenta Hirai - Web page: https://patentgrep.com/patent/US12603228B2 ## CPC - H01G 4/30: Stacked capacitors (H01G4/33 takes precedence) - H01G 4/008: Selection of materials - H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)} - H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor - H01G 4/2325: {characterised by the material of the terminals} - H01G 4/0085: {Fried electrodes} - H01G 4/012: Form of non-self-supporting electrodes - H01G 4/1227: {based on alkaline earth titanates} - H01G 4/1236: {based on zirconium oxides or zirconates (H01G4/1263 takes precedence)} - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) ## Abstract A multilayer ceramic capacitor includes a multilayer body including inner dielectric layers and internal electrode layers laminated therein, and external electrodes. Each of the inner dielectric layers includes a middle region at a middle portion and end regions at end portions in the length direction. A thickness of each of the inner dielectric layers is defined as Td, the middle region includes a first region with a dimension in the length direction of Td/2 and a dimension in the lamination direction of Td, and second regions adjacent to the first region with a dimension in the length direction of Td/2 and a dimension in the lamination direction of Td, the first region has a higher porosity than other regions, and a difference between a porosity in the first region and a porosity in each of the second regions is about 1% or more and about 5% or less. ## Claims ### Claim 1 A multilayer ceramic capacitor comprising: a multilayer body including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately laminated in a lamination direction, outer layer portions sandwiching the inner layer portion in the lamination direction, a first main surface and a second main surface opposed to each other in the lamination direction, a first lateral surface and a second lateral surface opposed to each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction; and a pair of external electrodes covering at least the first end surface and the second end surface and being connected to the plurality of internal electrode layers; wherein when viewed in a cross section parallel or substantially parallel to the length direction and the lamination direction, each of the plurality of inner dielectric layers includes a middle region at a middle portion in the length direction and end regions at end portions in the length direction; when a thickness of each of the plurality of inner dielectric layers in the lamination direction is defined as Td, the middle region includes a rectangular or substantially rectangular region A1 in which a dimension in the length direction is defined as Td/2 and a dimension in the lamination direction is defined as Td, and rectangular or substantially rectangular regions A2 each adjacent to the region A1 and in each of which a dimension in the length direction is defined as Td/2 and a dimension in the lamination direction is defined as Td, the region A1 has a higher porosity than other regions, and a difference between a porosity P1 in the region A1 and a porosity P2 in each of the region A2 is about 1% or more and about 5% or less; and each of the region A1 and the regions A2 overlaps with at least one of the plurality of internal electrode layers in the lamination direction. ### Claim 2 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein, when a height of the multilayer body in the lamination direction is defined as Ts, the region A1 and each of the regions A2 are provided in a range of a height of about Ts/10 positioned in a middle portion of the multilayer body in the lamination direction. ### Claim 3 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein dimensions of the multilayer ceramic capacitor are about 0.2 mm or more and about 10 mm or less in the length direction, about 0.1 mm or more and about 10 mm or less in the width direction, and about 0.1 mm or more and about 10 mm or less in the lamination direction. ### Claim 4 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein corner portions and ridge portions of the multilayer body are rounded. ### Claim 5 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of inner dielectric layers includes BaTiO3, CaTiO3, SrTiO3, of CaZrO3 as a main component. ### Claim 6 (depends on 5) The multilayer ceramic capacitor according to claim 5, wherein each of the plurality of inner dielectric layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent. ### Claim 7 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein a thickness of each of the plurality of inner dielectric layers is about 0.2 μm or more and about 15 μm or less. ### Claim 8 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of internal electrode layers includes at least one of Cu, Ag, Pd, Sn, or Au, or an alloy including at least one of Cu, Ag, Pd, Sn, or Au. ### Claim 9 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein a thickness of each of the plurality of internal electrode layers is about 0.2 μm or more and about 2.0 μm. ### Claim 10 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein a thickness of each of the plurality of internal electrode layers is about 0.3 μm or more and about 0.35 μm or less. ### Claim 11 (depends on 1) The multilayer ceramic capacitor according to claim 1, wherein each of the pair of first and second electrodes includes a base electrode layer and a plated layer. ### Claim 12 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein the base electrode layer includes metal and glass. ### Claim 13 (depends on 12) The multilayer ceramic capacitor according to claim 12, wherein a glass component of the glass of the base electrode layer includes at least one of B, Si, Ba, Mg, Al, or Li. ### Claim 14 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein the metal of the base electrode layer includes at least one of Ni, Ag, Pd, or Au, or an alloy including at least one of Ni, Ag, Pd, or Au. ### Claim 15 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein a thickness of the base electrode layer is about 2 μm or more and about 220 μm or less. ### Claim 16 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein the plated layer includes at least one of Cu, Ni, Ag, Pd, or Au, or an alloy including at least one of Cu, Ni, Ag, Pd, or Au. ### Claim 17 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein the plated layer includes a Ni plating and a Sn plating. ### Claim 18 (depends on 11) The multilayer ceramic capacitor according to claim 11, wherein the plated layer includes a Cu plating, a Ni plating, and a Sn plating.