# US 12,603,140 B2 · Soft programming method and erasing method for memory device

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- Number: US 12,603,140 B2
- Document ID: US12603140B2
- Status: Granted
- Kind: B2
- Application number: 18/754,159
- Filed: 2024-06-26
- Published: 2026-01-01
- Granted: 2026-04-14
- Earliest claimed: 2024-06-26
- Assignees: Macronix International Co., Ltd.
- Applicants: MACRONIX International Co., Ltd.
- Inventors: Chih-Wei Hu; Chih-Chang Hsieh; Teng-Hao Yeh; Hang-Ting Lue
- Web page: https://patentgrep.com/patent/US12603140B2

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/10: Programming or data input circuits
- G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A soft programming method and an erasing method for a memory device having n (positive integer) word lines are provided. The soft programming method includes: applying m (positive integer) programming pulses to the j-th word line of the n word lines, where j is a positive integer smaller than n; and determining an initial value of a programming pulse applied to the (j+1)-th to the n-th word lines based on a verification result of applying the m programming pulses to the j-th word line. When the i-th programming pulse, among the m programming pulses applied to the j-th word line, passes verification, the i-th programming pulse is set as the initial value of the programming pulse for the (j+1)-th to the n-th word lines, where i=1 to m. This method is also applicable to a 3D NAND flash memory. The memory device has high capacity and high performance.

## Claims

### Claim 1

A soft programming method for a memory device that comprises n word lines (n is a positive integer), the soft programming method comprising:
applying a pre-verification voltage to each of the n word lines;
applying m programming pulses (m is a positive integer) to a j-th word line among the n word lines, where j is a positive integer smaller than n,
wherein the j-th word line is a word line among the n word lines that firstly fails to pass the pre-verification voltage and starts to be applied with the m programming pulses; and
determining an initial value of a programming pulse applied to a (j+1)-th word line to an n-th word line based on a verification result of applying the m programming pulses to the j-th word line,
wherein in response to an i-th programming pulse, among the m programming pulses applied to the j-th word line, passing a verification, the i-th programming pulse is set as the initial value of the programming pulse applied to the (j+1)-th word line to the n-th word line, where i=1 to m.

### Claim 2 (depends on 1)

The soft programming method for the memory device according to claim 1, wherein the j-th word line is a first word line among the n word lines.

### Claim 3 (depends on 1)

The soft programming method for the memory device according to claim 1, further comprising:
sequentially applying the i-th programming pulse to an m-th programming pulse to each of the (j+1)-th word line to the n-th word line; and
further applying an i-th post verification voltage to an m-th post verification voltage after applying each of the i-th programming pulse to the m-th programming pulse.

### Claim 4 (depends on 3)

The soft programming method for the memory device according to claim 3, wherein at least one of verifications of the i-th post verification voltage to an (m-2)-th post verification voltage is not performed, where m-2>i.

### Claim 5 (depends on 1)

The soft programming method for the memory device according to claim 1, further comprising:
determining an initial value of a programming pulse applied to a (j+k+1)-th word line to the n-th word line based on the verification result of applying the m programming pulses to the j-th word line to a verification result of applying the m programming pulses to a (j+k)-th word line, where k is a positive integral and j+k<n.

### Claim 6 (depends on 1)

The soft programming method for the memory device according to claim 1, further comprising:
determining the initial value of the programming pulse applied to the (j+k+1)-th word line to the n-th word line by averaging the initial value of the programming pulse obtained based on the verification result of applying the m programming pulses to the j-th word line to an initial value of a programming pulse obtained based on the verification result of applying the m programming pulses to the (j+k)-th word line, where k is a positive integral and j+k<n.

### Claim 7 (depends on 6)

The soft programming method for the memory device according to claim 6, wherein averaging the initial value is performed by an arithmetic average.

### Claim 8 (depends on 1)

The soft programming method for the memory device according to claim 1, wherein the memory device is a 3D NOR flash memory.

### Claim 9

An erasing method for a memory device that comprises n word lines (n is a positive integer), the erasing method comprising:
applying an erase voltage to a plurality of memory cells on the n word lines to perform a block erase;
applying a pre-verification voltage to each of the n word lines;
applying m programming pulses (m is a positive integer) to a j-th word line among the n word lines, where j is a positive integer smaller than n,
wherein the j-th word line is a word line among the n word lines that firstly fails to pass the pre-verification voltage and starts to be applied with the m programming pulses; and
determining an initial value of a programming pulse applied to a (j+1)-th word line to an n-th word line based on a verification result of applying the m programming pulses to the j-th word line,
wherein in response to an i-th programming pulse, among the m programming pulses applied to the j-th word line, passing a verification, the i-th programming pulse is set as the initial value of the programming pulse applied to the (j+1)-th word line to the n-th word line, where i=1 to m.

### Claim 10 (depends on 9)

The erasing method for the memory device according to claim 9, wherein the j-th word line is a first word line among the n word lines.

### Claim 11 (depends on 9)

The erasing method for the memory device according to claim 9, further comprising:
sequentially applying the i-th programming pulse to an m-th programming pulse to each of the (j+1)-th word line to the n-th word line; and
further applying an i-th post verification voltage to an m-th post verification voltage after applying each of the i-th programming pulse to the m-th programming pulse.

### Claim 12 (depends on 11)

The erasing method for the memory device according to claim 11, wherein at least one of verifications of the i-th post verification voltage to an (m-2)-th post verification voltage is not performed, where m-2>i.

### Claim 13 (depends on 9)

The erasing method for the memory device according to claim 9, further comprising:
determining an initial value of a programming pulse applied to a (j+k+1)-th word line to the n-th word line based on the verification result of applying the m programming pulses to the j-th word line to a verification result of applying the m programming pulses to a (j+k)-th word line, where k is a positive integral and j+k<n.

### Claim 14 (depends on 9)

The erasing method for the memory device according to claim 9, further comprising:
determining the initial value of the programming pulse applied to the (j+k+1)-th word line to the n-th word line by averaging the initial value of the programming pulse obtained based on the verification result of applying the m programming pulses to the j-th word line to an initial value of a programming pulse obtained based on the verification result of applying the m programming pulses to the (j+k)-th word line, where k is a positive integral and j+k<n.

### Claim 15 (depends on 14)

The erasing method for the memory device according to claim 14, wherein averaging the initial value is performed by an arithmetic average.

### Claim 16 (depends on 9)

The erasing method for the memory device according to claim 9, wherein the memory device is a 3D NOR flash memory.