NOR memory cell with floating gate
AssigneeGreenliant IP LLC
InventorBing Yeh
Life of this patent
Estimating the term…
Abstract
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; an electrically conductive control gate; an electrically conductive word line; and a floating gate insulated from the substrate and the word line and comprising: a first tip substantially aligned with the sidewall portion of the trench region of the substrate; and a second tip self-aligned with an edge of the word line that is farthest from the second portion of the control gate.
Claims20
An electrically erasable programmable nonvolatile memory cell comprising:
- a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate;
- an electrically conductive control gate comprising:
- a first portion disposed inside the trench, insulated from the bottom portion and sidewall portion of the trench region of the substrate, and apart from a sidewall of the sidewall portion of the trench region by a first distance (A) in the lateral direction;
- and
- a second portion disposed above and extending away from the trench;
- an electrically conductive word line insulated from the control gate and offset from the second portion of the control gate by a second distance (B) greater than the first distance in the lateral direction;
- a floating gate insulated from the substrate and the word line and comprising:
- a first end, comprising a portion of the floating gate closest to the control gate, separated in the lateral direction from the second portion of the control gate by a third distance that is greater than the first distance and less than the second distance;
- and
- a second end self-aligned with an edge 132 of the word line that is farthest from the second portion of the control gate.
An electrically erasable programmable nonvolatile memory cell comprising:
- a semiconductor substrate having a bit line region, a surface region apart from the bit line region in a lateral direction, and a trench region apart from the surface region in the lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate;
- an electrically conductive control gate comprising:
- a first portion disposed inside the trench, insulated from the bottom portion and sidewall portion of the trench region of the substrate, and apart from the sidewall portion of the trench region by a first distance (A) in the lateral direction;
- and
- a second portion disposed above and extending away from the trench;
- an electrically conductive word line insulated from the control gate and offset from the second portion of the control gate by a second distance (B) greater than the first distance in the lateral direction;
- an electrically conductive floating gate insulated from the substrate and the word line and comprising:
- a first end comprising a portion of the floating gate closest to the control gate;
- and
- a second end self-aligned with an edge 132 of the word line that is farthest from the second portion of the control gate;
- a first indium implant disposed in a region of the substrate below the bottom portion of the trench region;
- and a second indium implant disposed in a region of the substrate adjacent to a bottom of a source or drain region of the memory cell.
Dependencies are inferred from the claim text.