# US 12,603,133 B2 · Slow charge loss monitor for power up performance boosting > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,133 B2 - Document ID: US12603133B2 - Status: Granted - Kind: B2 - Application number: 18/431,886 - Filed: 2024-02-02 - Published: 2024-08-15 - Granted: 2026-04-14 - Earliest claimed: 2023-02-09 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Nicola Ciocchini; Ugo Russo; Steven Michael Kientz - Web page: https://patentgrep.com/patent/US12603133B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 16/30: Power supply circuits - G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells. ## Claims ### Claim 1 A memory sub-system comprising: a memory device comprising a plurality of cells; and a processing device operatively coupled to the memory device, the processing device to perform operations comprising: responsive to detecting a power-off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a first voltage offset bin of a plurality of voltage offset bins, the first voltage offset bin associated with a specified subset of the plurality of cells based on a time after programming the specified subset of the plurality of cells, and wherein the first voltage offset bin defines a set of voltage offsets to be applied to a base read voltage level. ### Claim 2 (depends on 1) The memory sub-system of claim 1, the operations further comprising: determining, based on the voltage offset bin shift, a duration of a power-off state associated with the power-off event. ### Claim 3 (depends on 1) The memory sub-system of claim 1, the operations further comprising: determining a program temperature of the memory sub-system, wherein the program temperature corresponds to programming the dummy subset of the plurality of cells; identifying a power-up temperature of the memory sub-system, wherein the power-up temperature is associated with the power-up event; and adjusting the voltage offset bin shift based on a difference between the program temperature and the power-up temperature. ### Claim 4 (depends on 1) The memory sub-system of claim 1, the operations further comprising: updating an entry corresponding to the specified subset of the plurality of cells in a data structure, wherein the entry comprises a stored voltage offset bin. ### Claim 5 (depends on 1) The memory sub-system of claim 1, wherein identifying, based on the voltage shift, the voltage offset bin shift corresponding to the voltage offset bin associated with the specified subset of the plurality of cells further comprises: mapping, using a data structure, the voltage shift to the voltage offset bin shift. ### Claim 6 (depends on 1) The memory sub-system of claim 1, wherein determining the voltage shift associated with the dummy subset of the plurality of cells responsive to detecting the power-up event further comprises: determining a valley center of a highest voltage distribution valley of the plurality of cells; identifying a programming valley center of the highest voltage distribution valley for the predefined logical state programmed to the dummy subset of the plurality of cells; and determining the voltage shift based on a difference of the valley center and the programming valley center. ### Claim 7 (depends on 1) The memory sub-system of claim 1, wherein the power-off event comprises an asynchronous power event. ### Claim 8 A method comprising: responsive to detecting a power-off event, programming, to a predefined logical state, by a processing device, a dummy subset of a plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells based on a time after programming the specified subset of the plurality of cells, and wherein the first voltage offset bin defines a set of voltage offsets to be applied to a base read voltage level. ### Claim 9 (depends on 8) The method of claim 8, the method further comprising: determining, based on the voltage offset bin shift, a duration of a power-off state associated with the power-off event. ### Claim 10 (depends on 8) The method of claim 8, the method further comprising: determining a program temperature of the plurality of cells, wherein the program temperature corresponds to programming the dummy subset of the plurality of cells; identifying a power-up temperature of the plurality of cells, wherein the power-up temperature is associated with the power-up event; and adjusting the voltage offset bin shift based on a difference between the program temperature and the power-up temperature. ### Claim 11 (depends on 8) The method of claim 8, the method further comprising: updating an entry corresponding to the specified subset of the plurality of cells in a data structure, wherein the entry comprises a stored voltage offset bin. ### Claim 12 (depends on 8) The method of claim 8, wherein identifying, based on the voltage shift, the voltage offset bin shift corresponding to the voltage offset bin associated with the specified subset of the plurality of cells further comprises: mapping, using a data structure, the voltage shift to the voltage offset bin shift. ### Claim 13 (depends on 8) The method of claim 8, wherein determining the voltage shift associated with the dummy subset of the plurality of cells responsive to detecting the power-up event further comprises: determining a valley center of a highest voltage distribution valley of the plurality of cells; identifying a programming valley center of the highest voltage distribution valley for the predefined logical state programmed to the dummy subset of the plurality of cells; and determining the voltage shift based on a difference of the valley center and the programming valley center. ### Claim 14 (depends on 8) The method of claim 8, wherein the power-off event comprises an asynchronous power event. ### Claim 15 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: responsive to detecting a power-off event, programming, to a predefined logical state, a dummy subset of a plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells based on a time after programming the specified subset of the plurality of cells, and wherein the first voltage offset bin defines a set of voltage offsets to be applied to a base read voltage level. ### Claim 16 (depends on 15) The non-transitory computer-readable storage medium of claim 15, the operations further comprising: determining, based on the voltage offset bin shift, a duration of a power-off state associated with the power-off event; and determining a program temperature of the plurality of cells, wherein the program temperature corresponds to programming the dummy subset of the plurality of cells; identifying a power-up temperature of the plurality of cells, wherein the power-up temperature is associated with the power-up event; and adjusting the voltage offset bin shift based on a difference between the program temperature and the power-up temperature. ### Claim 17 (depends on 15) The non-transitory computer-readable storage medium of claim 15, the operations further comprising: updating an entry corresponding to the specified subset of the plurality of cells in a data structure, wherein the entry comprises a stored voltage offset bin. ### Claim 18 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein identifying, based on the voltage shift, the voltage offset bin shift corresponding to the voltage offset bin associated with the specified subset of the plurality of cells further comprises: mapping, using a data structure, the voltage shift to the voltage offset bin shift. ### Claim 19 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein determining the voltage shift associated with the dummy subset of the plurality of cells responsive to detecting the power-up event further comprises: determining a valley center of a highest voltage distribution valley of the plurality of cells; identifying a programming valley center of the highest voltage distribution valley for the predefined logical state programmed to the dummy subset of the plurality of cells; and determining the voltage shift based on a difference of the valley center and the programming valley center. ### Claim 20 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the power-off event comprises an asynchronous power event.