Gate-controlled thyristor and CAM array

A content-addressable memory array of an NOR type, the content-addressable memory array comprising:

• a plurality of match lines, disposed to be substantially parallel in a column direction;
• a plurality of search lines, disposed to be substantially parallel in a row direction;
• and
• a plurality of content-addressable memory cells, each comprising a gate-controlled thyristor, wherein the content-addressable memory cells is respectively disposed at intersections of the match lines and the search lines,
• wherein each of the gate-controlled thyristors comprises:
• a first transistor, having a control end, a first end, and a second end, wherein the second end is connected to a ground potential;
• a second transistor, having a control end, a first end, and a second end, wherein the control end is connected to a fixed bias voltage, the second end is connected to the first end of the first transistor, and the second transistor is configured to store data;
• and
• a third transistor, having a control end, a first end, and a second end, wherein the second end is connected to the first end of the second transistor,
• wherein the first end of the third transistor of each gate-controlled thyristor in a same row in the row direction, among the gate-controlled thyristors, is connected to a corresponding match line of the match lines,
• wherein the first end of the third transistor connected to the match line is a P+ junction region, and the second end of the first transistor connected to the ground potential is a N+ junction region,
• the control end of the first transistor and the control end of the third transistor of each gate-controlled thyristor in a same column of the column direction, among the gate-controlled thyristors, are connected to a corresponding search line of the search lines, and
• for a selected gate-controlled thyristor among the gate-controlled thyristors, a search bit is determined based on a search line voltage applied to the corresponding search line, and the search bit and the data are compared to determine whether the search bit matches the data.

A content-addressable memory array of a NAND type, the content-addressable memory array comprising:

• a plurality of match lines;
• a plurality of search lines;
• and
• a plurality of content-addressable memory cells, each comprising a gate-controlled thyristor, wherein the content-addressable memory cells are arranged to extend along a column direction and a row direction to form a memory array,
• wherein each of the gate-controlled thyristors comprises:
• a first transistor, having a control end, a first end and a second end;
• a second transistor, having a control end, a first end, and a second end, wherein the control end is connected to a fixed bias voltage, the second end is connected to the first end of the first transistor, and the second transistor is configured to store data;
• and
• a third transistor, having a control end, a first end, and a second end, wherein the second end is connected to the first end of the second transistor,
• wherein the first end of the third transistor connected to the match line is a P+ junction region, and the second end of the first transistor connected to the ground potential is a N+ junction region,
• wherein a plurality of gate-controlled thyristors in a same column in the row direction, among the gate-controlled thyristors, are connected with each other in series, the first end of the third transistor of a first gate-controlled thyristor among the gate-controlled thyristors in the same column is connected to a corresponding match line of the plurality of match lines, and the second end of the first transistor of a final gate-controlled thyristor among the gate-controlled thyristors in the same column is connected to the ground potential,
• the control end of the first transistor and the control end of the third transistor of each of a plurality of gate-controlled thyristors in a same row in the column direction, among the gate-controlled thyristors, are connected to a corresponding search line of the plurality of search lines, and
• for a selected gate-controlled thyristor among the gate-controlled thyristors, a search bit is determined based on a search line voltage applied to the corresponding search line, and the search bit and the data are compared to determine whether the search bit matches the data.