# US 12,603,130 B2 · Memory and reading, writing and erasing methods thereof

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- Number: US 12,603,130 B2
- Document ID: US12603130B2
- Status: Granted
- Kind: B2
- Application number: 18/690,274
- Filed: 2021-12-31
- Published: 2024-11-14
- Granted: 2026-04-14
- Earliest claimed: 2021-09-08
- Assignees: Shanghai Ic R&D Center Co., Ltd
- Applicants: Shanghai Ic R&D Center Co., Ltd.
- Inventors: Lingyi Guo; Xueru Yu
- Web page: https://patentgrep.com/patent/US12603130B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.

## Claims

### Claim 1

A memory, comprising:
H memory planes arranged in parallel along a first direction, wherein each memory plane extends in a second direction, and the memory plane comprises M columns of memory strings; the memory strings extend in a third direction; the first direction, the second direction and the third direction are different; and H and M are integers greater than zero;
wherein a single column of memory string comprises:
N rows of memristive memory cells connected in sequence, wherein N is an integer greater than zero;
N word lines, wherein a single word line is connected to corresponding rows of memristive memory cells; the word lines are used to receive word line voltages; and memristive memory cells in same rows receive a same word line voltage;
gating transistors, wherein sources of the gating transistors are connected to memristive memory cells in first rows;
gating lines, connected to gates of the gating transistors for receiving gating voltages, wherein all gating transistors on a memory plane receive a same gating voltage;
bit lines, connected to drains of the gating transistors for receiving bit line voltages, wherein gating transistors in same columns on different memory planes receive a same bit line voltage;
a common source line, wherein memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor.

### Claim 2 (depends on 1)

The memory according to claim 1, wherein each memristive memory cell comprises a transistor and a memristor; a first end of the memristor is connected to a source of the transistor, and a second end of the memristor is connected to second ends of all memristors of a same memory string; the source of the transistor is connected to a drain of an adjacent transistor of the same memory string, and a source of a transistor in a last row of the memory string is connected to the common source line;
a word line is connected to a gate of the transistor.

### Claim 3 (depends on 2)

The memory according to claim 2, wherein when a memristive memory cell to be read is located in a k-th row of a j-th memory string on an i-th memory plane, a voltage at a bit line corresponding to the j-th memory string is a bit line active voltage; voltages at other bit lines are bit line inactive voltages;
all gating transistors on the i-th memory plane is turned on, and other gating transistors are turned off;
when k=1, a transistor comprised in the memristive memory cell to be read is turned on, and no current exists in other transistors; the memristive memory cell to be read is connected to a gating transistor;
when k>1, during a first reading cycle, transistors comprised in memristive memory cells in a first row to a (k−1)-th row of the j-th memory string are all turned on first; and during a second reading cycle, transistors in the first row to the k-th row of the j-th memory string are turned on, and no current exists in other transistors;
wherein i, j and k are all integers greater than zero, and i≤H, j≤M, k≤N.

### Claim 4 (depends on 2)

The memory according to claim 2, wherein when memristive memory cells to be read are located in a first row to an n-th row of a j-th memory string on an i-th memory plane, a voltage at a bit line corresponding to the j-th memory string is a bit line active voltage; voltages at other bit lines are bit line inactive voltages;
all gating transistors on the i-th memory plane are turned on, and other gating transistors are turned off;
transistors comprised in the memristive memory cells to be read are turned in sequence;
wherein i, j and n are all integers greater than zero, and i≤H, j≤M, 1<n≤N.

### Claim 5 (depends on 2)

The memory according to claim 2, wherein when k>1, a target resistance value is to be written to a memristive memory cell to be written; and when the memristive memory cell to be written is located in a k-th row of a j-th memory string on an i-th memory plane, original resistance values corresponding to memristive memory cells in a first row to a (k−1)-th row of the j-th memory string on the i-th memory plane are read and saved; a level difference is determined according to the target resistance value; the level difference is set between the common source line and a bit line corresponding to the j-th memory string; each word line corresponding to the first row to the k-th row of the j-th memory string has a word line level, wherein the level difference and word line levels are used to turn on transistors comprised in the memristive memory cells in the first row to the k-th row;
except for the memristive memory cells in the first row to the k-th row, no current exists in other transistors;
all gating transistors on the i-th memory plane are turned on, and other gating transistors are turned off; at the same time as writing to the memristive memory cell to be written, the memristive memory cells in the first row to the (k−1)-th row of the j-th memory string on the i-th memory plane are also written to, wherein each memristive memory cell has the target resistance value of the k-th row after being written to; by taking the original resistance values corresponding to the memristive memory cells in the (k−1)-th row to the first row of the j-th memory string on the i-th memory plane as corresponding target resistance values, the memristive memory cells in the (k−1)-th row to the first row of the j-th memory string on the i-th memory plane are rewritten to in sequence;
wherein i, j and k are all integers greater than zero, and i≤H, j≤M, k≤N.

### Claim 6 (depends on 2)

The memory according to claim 2, wherein when a memory string to be erased is a j-th memory string on an i-th memory plane, there is a level difference between the common source line and a bit line corresponding to the j-th memory string; each word line corresponding to the j-th memory string has a word line level, wherein the level difference and word line levels are used to turn on each of transistors of the j-th memory string;
all gating transistors on the i-th memory plane are turned on, and other gating transistors are turned off;
and, except for the j-th memory string on the i-th memory plane, no current exists in other transistors;
wherein i and j are all integers greater than zero, and i≤H, j≤M.

### Claim 7 (depends on 1)

A memory reading method, applied to the memory according to claim 1, wherein when a memristive memory cell to be read is located in a k-th row of a j-th memory string on an i-th memory plane, the method comprises:
inputting a bit line active voltage at a bit line corresponding to the j-th memory string;
except for the j-th memory string and memory strings in same columns as the j-th memory string, inputting bit line inactive voltages at bit lines corresponding to other memory strings;
turning on all gating transistors on the i-th memory plane, and turning off other gating transistors;
before reading, making no current exist in transistors comprised in all memristive memory cells comprised in the memory;
after starting reading, when k=1, turning on a transistor comprised in the memristive memory cell to be read;
when k>1, during a first reading cycle, turning on transistors comprised in memristive memory cells in a first row to a (k−1)-th row of the j-th memory string on the i-th memory plane; and during a second reading cycle, turning on transistors comprised in memristive memory cells in the first row to the k-th row of the j-th memory string on the i-th memory plane;
wherein i, j and k are all integers greater than zero, and i≤H, j≤M and k≤N.

### Claim 8 (depends on 7)

The memory reading method according to claim 7, wherein when k=1, a resistance value of a memristor included in the memristive memory cell to be read is determined according to a formula
R
1
=
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
1
V
1
-
V
ref
⁢
R
ref
,
wherein R1 represents the resistance value of the memristor comprised in the memristive memory cell to be read, Vbl_read_active is the bit line active voltage at the bit line corresponding to the j-th memory string, V1 is a voltage at the common source line when reading from the memristive memory cell to be read, Rref is a resistance value of the reference resistor, and Vref represents a potential difference between the reference potential and ground;
when k>1, the resistance value of the memristor comprised in the memristive memory cell to be read is determined according to a formula
R
k
=
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
k
)
⁢
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
k
-
1
)
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
ref
)
⁢
(
V
k
-
V
k
-
1
)
⁢
R
ref
,
wherein Rk represents the resistance value of the memristor comprised in the memristive memory cell to be read, Vbl_read_active is the bit line active voltage at the bit line corresponding to the j-th memory string, Vk-1 is a voltage at the common source line during the first reading cycle, and Vk is a voltage at the common source line during the second reading cycle.

### Claim 9 (depends on 1)

A memory reading method, applied to the memory according to claim 1, wherein when memristive memory cells to be read are located in a first row to an n-th row of a j-th memory string on an i-th memory plane, the method comprises:
inputting a bit line active voltage at a bit line corresponding to the j th memory string; inputting bit line inactive voltages at other bit lines;
turning on all gating transistors on the i-th memory plane, and turning off other gating transistors;
before reading, making no current exist in transistors comprised in all memristive memory cells in the memory;
after starting reading, during an x-th reading cycle, turning on transistors comprised in memristive memory cells in the first row to an x-th row of the j-th memory string on the i-th memory plane, wherein a total of n reading cycles are required;
wherein i, j, n and x are all integers greater than zero, and i≤H, j≤M, 1<n≤N, 1≤x≤n.

### Claim 10 (depends on 9)

The memory reading method according to claim 9, wherein a resistance value of a memristor in the first row comprised in the memristive memory cells to be read is determined according to a formula
R
1
=
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
1
V
1
-
V
ref
⁢
R
ref
;
wherein R1 represents the resistance value of the memristor in the first row comprised in the memristive memory cells to be read, Vbl_read_active is the bit line active voltage at the bit line corresponding to the j-th memory string, V1 is a voltage at the common source line during a first reading cycle, Rref is a resistance value of the reference resistor, and Vref represents a potential difference between the reference potential and ground;
a resistance value of a memristor in the x-th row comprised in the memristive memory cells to be read is determined according to a formula
R
x
=
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
x
)
⁢
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
x
-
1
)
(
V
bl
⁢
_
⁢
read
⁢
_
⁢
active
-
V
ref
)
⁢
(
V
x
-
V
x
-
1
)
⁢
R
ref
,
wherein Rx represents the resistance value of the memristor comprised in the memristive memory cell in the x-th row comprised in the memristive memory cells to be read, Vbl_read_active is the bit line active voltage at the bit line corresponding to the j-th memory string, Vx-1 is a voltage at the common source line during an (x−1)-th reading cycle, and Vx is a voltage at the common source line during the x-th reading cycle.

### Claim 11 (depends on 1)

A memory writing method, applied to the memory according to claim 1, wherein a target resistance value is to be written to a memristive memory cell to be written, and when a memristive memory cell to be written is located in a k-th row of a j-th memory string on an i-th memory plane, the method comprises:
determining a level difference according to the target resistance value, and setting the level difference between the common source line and a bit line corresponding to the j-th memory string, wherein each word line corresponding to a first row to the k-th row of the j-th memory string has a word line level, and the level difference and word line levels are used to turn on transistors comprised in memristive memory cells in the first row to the k-th row;
turning on all gating transistors on the i-th memory plane, and turning off other gating transistors;
wherein except for the memristive memory cells in the first row to the k-th row, no current exists in other transistors;
wherein i, j and k are all integers greater than zero, and i≤H, j≤M, k≤N.

### Claim 12 (depends on 11)

The memory writing method according to claim 11, further comprising:
when k>1, determining the level difference according to the target resistance value, and before setting the level difference between the common source line and the bit line corresponding to the j-th memory string, reading and saving original resistance values of memristive memory cells in the first row to a (k−1)-th row of the j-th memory string on the i-th memory plane;
wherein i, j, k and x are all integers greater than zero, and i≤H, j≤M, 1<k≤N, 1≤x≤k−1.

### Claim 13 (depends on 12)

The memory writing method according to claim 12, wherein at the same time as writing to the memristive memory cells to be written, the memristive memory cells in the first row to the (k−1)-th row of the j-th memory string on the i-th memory plane are also written to, and the target resistance value of the k-th row is to be written to each memristive memory cell.

### Claim 14 (depends on 1)

A memory erasing method, applied to the memory according to claim 1, wherein when a memory string to be erased is a j-th memory string corresponding to an i-th memory plane, the method comprises:
setting a level difference between the common source line and a bit line corresponding to the j-th memory string, wherein each word line corresponding to the j-th memory string has a word line level, and the level difference and word line levels are used to turn on each transistor corresponding to the j-th memory string;
turning on all gating transistors corresponding to the i-th memory plane; and turning off other gating transistors;
wherein except for the j-th memory string, no current exists in other transistors.

### Claim 15 (depends on 12)

The memory writing method according to claim 12, wherein reading and saving the original resistance values of the memristive memory cells in the first row to the (k−1)-th row of the j-th memory string on the i-th memory plane comprises:
inputting a bit line active voltage at the bit line corresponding to the j-th memory string; inputting bit line inactive voltages at others bit lines;
turning on all gating transistors on the i-th memory plane, and turning off other gating transistors;
before reading, making no current exist in transistors comprised in all memristive memory cells in the memory;
after starting reading, during an x-th reading cycle, turning on transistors comprised in memristive memory cells in the first row to an x-th row of the j-th memory string on the i-th memory plane;
wherein i, j, k and x are all integers greater than zero, and i≤H, j≤M, 1<k≤N, 1≤x≤k−1.

### Claim 16 (depends on 12)

The memory writing method according to claim 12, wherein after turning on all gating transistors on the i-th memory plane and turning off the other gating transistors, the method further comprises: by taking the original resistance values corresponding to the memristive memory cells in the (k−1)-th row to the first row of the j-th memory string on the i-th memory plane as corresponding target resistance values, rewriting to the memristive memory cells in the (k−1)-th row to the first row of the j-th memory string on the i-th memory plane in sequence.

### Claim 17 (depends on 16)

The memory writing method according to claim 16, wherein steps of rewriting to the memristive memory cells in the (k−1)-th row to the first row of the j-th memory string on the i-th memory plane in sequence are identical with steps of writing to the memristive memory cell to be written in the k-th row of a j-th memory string on the i-th memory plane.