# US 12,603,129 B2 · Ramp-based biasing in a memory device

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- Number: US 12,603,129 B2
- Document ID: US12603129B2
- Status: Granted
- Kind: B2
- Application number: 18/457,188
- Filed: 2023-08-28
- Published: 2023-12-14
- Granted: 2026-04-14
- Earliest claimed: 2020-09-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hari Giduturi
- Web page: https://patentgrep.com/patent/US12603129B2

## CPC

- G11C 11/1655: {Bit-line or column circuits}
- G11C 13/003: {Cell access}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 11/1653: {Address circuits or decoders}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1659: {Cell access}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 11/1693: {Timing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 2213/71: Three dimensional array
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

## Claims

### Claim 1

A method, comprising:
biasing, using one or more biasing circuits, a first voltage using a first waveshape;
activating a first memory cell using the first voltage;
biasing, using the one or more biasing circuits, a second voltage using a second waveshape; and
activating a second memory cell using the second voltage, wherein the second waveshape is different from the first waveshape, and the first and second waveshapes are based at least in part on respective distances of the memory cells from respective drivers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first memory cell and the second memory cell share a driver and an access line coupled to the driver.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first waveshape comprises a smaller slope than the second waveshape, and the first memory cell is closer to the driver than the second memory cell is to the driver.

### Claim 4 (depends on 1)

The method of claim 1, comprising biasing, using the one or more biasing circuits, a third voltage using a third waveshape, wherein the third waveshape has a peak magnitude in a different direction than the first waveshape, and wherein activating the first memory cell using the first voltage includes using the third voltage.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first and third waveshapes have the same magnitude but different directions.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first waveshape and the second waveshape have different ramp rates.

### Claim 7 (depends on 1)

The method of claim 1, comprising using control circuitry to set a trim signal to generate the first and second waveshapes based at least in part on locations of the memory cells.

### Claim 8

A memory device, comprising:
a plurality of access lines arranged in an array;
a plurality of memory cells configured to be accessed via the plurality of access lines;
variable biasing circuitry configured to bias a voltage on an access line of the plurality of access lines to change a waveshape of the voltage on the access line; and
a control circuit configured to set the waveshape of the variable biasing circuitry based at least in part on a distance from a memory cell of the plurality of memory cells to a corresponding driver.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein setting the waveshape comprises adjusting a current of a variable current source by transmitting a trim current input from the control circuit to the variable current source.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein setting the waveshape comprises adjusting a capacitance of a variable capacitor by transmitting a trim capacitance input from the control circuit to the variable current source.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein setting the waveshape comprises setting a width of an enable signal applied to a gate of a transistor coupled to the variable current source.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the transistor is configured to selectively couple and decouple the variable current source from a ramp signal.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the control circuit is configured to clamp the voltage using the variable biasing circuitry in response to activation of the memory cell.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the variable capacitor is coupled between the ramp signal and ground.

### Claim 15 (depends on 8)

The memory device of claim 8, comprising a snap detector configured to detect when the memory cell is activated.

### Claim 16

A memory device, comprising:
a plurality of access lines arranged in an array;
a plurality of memory cells configured to be accessed via the plurality of access lines;
variable biasing circuitry configured to:
bias a first voltage using a first waveshape to cause a first memory cell to be activated using the first voltage; and
bias a second voltage using a second waveshape to cause a second memory cell to be activated using the second voltage, wherein the first and second waveshapes are different from each other and are based at least in part on respective distances of the first and second memory cells from respective memory drivers.

### Claim 17 (depends on 16)

The memory device of claim 16, comprising a control circuit configured to set the first and second waveshapes of the variable biasing circuitry based at least in part on the respective distances.

### Claim 18 (depends on 16)

The memory device of claim 16, wherein the first memory cell and the second memory cell share a driver and an access line coupled to the driver.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the first waveshape comprises a smaller slope than the second waveshape, and the first memory cell is closer to the driver than the second memory cell is to the driver.

### Claim 20 (depends on 16)

The memory device of claim 16, wherein the variable biasing circuitry is configured to bias a third voltage using a third waveshape, wherein the third waveshape has a peak magnitude in a different direction than the first waveshape, and wherein activating the first memory cell using the first voltage includes using the third voltage.