Read and write enhancements for arrays of superconducting memory cells

A method of reading and writing a superconducting memory circuit, the memory circuit comprising a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, a plurality of write word lines, and a plurality of dual-ported superconducting memory cells arranged into columns, wherein the plurality of write bit lines are greater in number than the plurality of read bit lines and their associated columns by at least a factor of two, the method comprising:

• configuring a read port of each of the plurality of dual-ported superconducting memory cells to be connected to a corresponding one of the plurality of read word lines and a corresponding one of the plurality of read bit lines;
• configuring a write port of each of the plurality of dual-ported superconducting memory cells to be connected to a corresponding one of the plurality of write word lines and a corresponding one of the plurality of write bit lines;
• connecting each of the plurality of dual-ported superconducting memory cells in a given column to a corresponding one of the plurality of read bit lines;
• connecting each of the plurality of read word lines to one of the plurality of dual-ported superconducting memory cells in a column;
• connecting each of the plurality of write word lines to a unique subset of the plurality of dual-ported superconducting memory cells of a given column;
• writing the superconducting memory circuit in one native write cycle;
• and
• reading the superconducting memory circuit in a plurality of native ready cycles,
• wherein the native read cycles and native write cycles are configured to correspond to prescribed parameters associated with a given type of the plurality of dual-ported superconducting memory cells.

A method of forming a superconducting memory circuit, the method comprising:

• forming a plurality of write word lines arranged in a first dimension in the superconducting memory circuit;
• forming a plurality of write bit lines arranged in a second dimension in the superconducting memory circuit, the first and second dimensions being different relative to one another;
• forming a plurality of superconducting memory cells arranged into a plurality of rows and columns, a first subset of the superconducting memory cells arranged in a same row being coupled with a common one of the plurality of write word lines, and at least two of the plurality of superconducting memory cells being coupled with different write word lines, and being coupled to a common one of the plurality of write bit lines;
• electrically connecting together a subset of the plurality of write bit lines that are proximate to one another by at least one operable wrap-around connection;
• configuring the superconducting memory circuit such that a bit signal of a first one of the write bit lines of the subset operably writes a state in a selected memory cell of a plurality of superconducting memory cells connected to all proximate write bit lines electrically connected together by the at least one wrap-around connection, and a write signal, representing a state, moves through at least a first proximate write bit line of the subset in one direction, and then when electrically connected to a second write bit line by the at least one wrap-around connection, reverses its direction of propagation relative to the first proximate write bit line of the subset.