# US 12,603,125 B2 · Self-timing read termination > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,125 B2 - Document ID: US12603125B2 - Status: Granted - Kind: B2 - Application number: 18/763,964 - Filed: 2024-07-03 - Published: 2025-01-16 - Granted: 2026-04-14 - Earliest claimed: 2023-07-11 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Milena Tsvetkova Ivanov; Stefanie Christina Granato; Jun Tan; Varsha Mohan; Manfred Hans Plan; Martin Brox; Morshed Mohammed; Yu Ting Wu; Juan Antonio Garrido Ocon - Web page: https://patentgrep.com/patent/US12603125B2 ## CPC - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/4094: Bit-line management or control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices implementing self-timing read termination are described. A memory system may perform a read operation in which the memory system generates a first signal and a second signal to couple a first sense component and a second sense component with a global access line, respectively. The first sense component may be coupled with one or more memory cells via an access line, and the second sense component may be configured to determine one or more logic values of the one or more memory cells based on the coupling with the global access line. The memory system may support a self-timed termination of the first signal to decouple the first sense component from the global access line. The memory system may generate a third signal to terminate the first signal based on determining the one or more logic values. ## Claims ### Claim 1 An apparatus, comprising: at least one memory device comprising a volatile memory array; and at least one controller coupled with the at least one memory device and configured to cause the apparatus to: receive a command to read data from one or more memory cells of the volatile memory array, the one or more memory cells coupled with a first access line, which is coupled with a first sense component; generate, based at least in part on the command, a first signal to couple the first sense component with a second access line; generate, based at least in part on the command, a second signal to couple the second access line with a second sense component during at least a portion of a duration that the second access line is coupled with the first sense component; determine, by the second sense component, one or more logic values of the one or more memory cells based at least in part on coupling the second sense component with the second access line; generate a third signal to terminate the first signal based at least in part on determining the one or more logic values by the second sense component; and terminate the first signal based at least in part on the third signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the third signal is generated by the second sense component, and the at least one controller is further configured to cause the apparatus to: output the third signal from the second sense component to a decoder coupled with the first sense component that generates the first signal, wherein the first signal is terminated based at least in part on outputting the third signal to the decoder. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: detect, via a sensor while the second sense component is coupled with the second access line, that a voltage of the second access line satisfies a threshold voltage, wherein the third signal is generated by the sensor based at least in part on the voltage satisfying the threshold voltage; and output the third signal from the sensor to a decoder coupled with the first sense component that generates the first signal, wherein the first signal is terminated based at least in part on outputting the third signal to the decoder. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the at least one controller is further configured to cause the apparatus to: output, from the sensor to the second sense component, a fourth signal indicate that the voltage satisfies the threshold voltage, wherein the one or more logic values are determined by the second sense component based at least in part on receiving the fourth signal. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the voltage satisfying the threshold voltage comprises the voltage of the second access line dropping to or below the threshold voltage. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein, to terminate the first signal, the at least one controller is configured to cause the apparatus to: terminate, by a decoder coupled with the first sense component, the first signal responsive to receiving the third signal at the decoder to decouple the second access line from the first sense component. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: output, by the second sense component, an indication of the one or more logic values based at least in part on determining the one or more logic values, wherein the third signal is generated based at least in part on outputting the indication. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: output, by a decoder, the first signal to the first sense component via a column select line, wherein the first signal be generated by the decoder based at least in part on receiving the command at the decoder; and output, by the decoder, the second signal to the second sense component via a read control line, wherein the second signal is generated by the decoder based at least in part on receiving the command at the decoder. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the first signal is a column select signal and the second signal is a read control signal. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the third signal is generated concurrent with the determination of the one or more logic values. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: pre-charge, after terminating the first signal, the second access line from a first voltage to a second voltage, wherein a difference between the first voltage and the second voltage is based at least in part on generating the third signal. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the first access line is a bit line and the second access line is a global bit line. ### Claim 13 A method, comprising: receiving a command to read data from one or more memory cells of a volatile memory array, the one or more memory cells coupled with a first access line, which is coupled with a first sense component; generating, based at least in part on the command, a first signal to couple the first sense component with a second access line; generating, based at least in part on the command, a second signal to couple the second access line with a second sense component during at least a portion of a duration that the second access line is coupled with the first sense component; determining, by the second sense component, one or more logic values of the one or more memory cells based at least in part on coupling the second sense component with the second access line; generating a third signal to terminate the first signal based at least in part on determining the one or more logic values by the second sense component; and terminating the first signal based at least in part on the third signal. ### Claim 14 (depends on 13) The method of claim 13, wherein the third signal is generated by the second sense component, the method further comprising: outputting the third signal from the second sense component to a decoder coupled with the first sense component that generates the first signal, wherein the first signal is terminated based at least in part on outputting the third signal to the decoder. ### Claim 15 (depends on 13) The method of claim 13, further comprising: detecting, via a sensor while the second sense component is coupled with the second access line, that a voltage of the second access line satisfies a threshold voltage, wherein the third signal is generated by the sensor based at least in part on the voltage satisfying the threshold voltage; and outputting the third signal from the sensor to a decoder coupled with the first sense component that generates the first signal, wherein the first signal is terminated based at least in part on outputting the third signal to the decoder. ### Claim 16 (depends on 15) The method of claim 15, further comprising: outputting, from the sensor to the second sense component, a fourth signal indicate that the voltage satisfies the threshold voltage, wherein the one or more logic values are determined by the second sense component based at least in part on receiving the fourth signal. ### Claim 17 (depends on 13) The method of claim 13, further comprising: terminating, by a decoder coupled with the first sense component, the first signal responsive to receiving the third signal at the decoder to decouple the second access line from the first sense component. ### Claim 18 (depends on 13) The method of claim 13, further comprising: outputting, by the second sense component, an indication of the one or more logic values based at least in part on determining the one or more logic values, wherein the third signal is generated based at least in part on outputting the indication. ### Claim 19 (depends on 13) The method of claim 13, further comprising: outputting, by a decoder, the first signal to the first sense component via a column select line, wherein the first signal be generated by the decoder based at least in part on receiving the command at the decoder; and output, by the decoder, the second signal to the second sense component via a read control line, wherein the second signal is generated by the decoder based at least in part on receiving the command at the decoder. ### Claim 20 A non-transitory computer-readable medium storing code, the code comprising instructions executable by at least one processor to: receive a command to read data from one or more memory cells of a volatile memory array, the one or more memory cells coupled with a first access line, which is coupled with a first sense component; generate, based at least in part on the command, a first signal to couple the first sense component with a second access line; generate, based at least in part on the command, a second signal to couple the second access line with a second sense component during at least a portion of a duration that the second access line is coupled with the first sense component; determine, by the second sense component, one or more logic values of the one or more memory cells based at least in part on coupling the second sense component with the second access line; generate a third signal to terminate the first signal based at least in part on determining the one or more logic values by the second sense component; and terminate the first signal based at least in part on the third signal.