# US 12,603,122 B2 · Parallel pipe latch for memory access operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,122 B2 - Document ID: US12603122B2 - Status: Granted - Kind: B2 - Application number: 17/900,075 - Filed: 2022-08-31 - Published: 2024-02-29 - Granted: 2026-04-14 - Earliest claimed: 2022-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Jaeil Kim - Web page: https://patentgrep.com/patent/US12603122B2 ## CPC - G11C 11/409: Read-write [R-W] circuits - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipe latch circuitry and error correction code (ECC) circuitry. The memory device further includes pipe latch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry. ## Claims ### Claim 1 A memory device comprising: memory configured to store electronic data; pipe latch circuitry; and control circuitry configured to: receive a memory access command to access multiple bits of the electronic data stored in the memory; and responsive to receiving the memory access command to access the memory, provide one of data read from the memory as read command data or data to be written to the memory as write command data from the control circuitry to the pipe latch circuitry and to error correction code (ECC) circuitry; wherein the pipe latch circuitry includes multiple parallel pipe latches in a bitslice area of the memory, wherein each respective bitslice area includes one or more circuit elements that are repeated for each bit associated with the memory access command, and wherein the multiple parallel pipe latches are configured to maintain the read command data or the write command data for different sequential memory access operations transferred via a shared data path, and wherein the pipe latch circuitry is configured to: receive, via the shared data path, the read command data or the write command data from the control circuitry; operate the multiple parallel pipe latches in parallel to handle consecutive memory access commands with a fixed timing interval between commands; for write operations, latch the write command data while the ECC circuitry determines an error correction code; and for read operations, latch the read command data while the ECC circuitry performs an error correction operation, and maintain the read command data for a duration longer than a time to perform the error correction operation. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the pipe latch circuitry includes at least three pipe latches. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the at least three pipe latches are parallel to each other. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the pipe latch circuitry is configured to handle both the read command data and the write command data within one set of pipe latches. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the pipe latch circuitry is within a bank area of the memory. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the memory comprises dynamic random access memory (DRAM) or ferroelectric random access memory (FeRAM). ### Claim 7 (depends on 1) The memory device of claim 1, wherein the bitslice area of the memory is located outside a memory array area of the memory. ### Claim 8 (depends on 6) The memory device of claim 6, wherein the memory comprises a plurality of banks. ### Claim 9 A system comprising: a host device; a memory device coupled to the host device, the memory device comprising: memory; pipe latch circuitry; and control circuitry configured to: receive a memory access command to access multiple bits of electronic data stored in the memory; and responsive to receiving the memory access command to access the memory, provide one of data read from the memory as read command data or data to be written to the memory as write command data from the control circuitry to the pipe latch circuitry and to error correction code (ECC) circuitry; wherein the pipe latch circuitry includes multiple parallel pipe latches in a bitslice area of the memory, wherein each respective bitslice area includes one or more circuit elements that are repeated for each bit associated with the memory access command, and wherein the multiple parallel pipe latches are configured to maintain the read command data or the write command data for different sequential memory access operations transferred via a shared data path, and wherein the pipe latch circuitry is configured to: receive, via the shared data path, the read command data or the write command data from the control circuitry; operate the multiple parallel pipe latches in parallel to handle consecutive memory access commands with a fixed timing interval between commands; for write operations, latch the write command data while the ECC circuitry determines an error correction code; and for read operations, latch the read command data while the ECC circuitry performs an error correction operation, and maintain the read command data for a period of time of a duration longer than error calculation time of the ECC circuitry. ### Claim 10 (depends on 9) The system of claim 9, wherein the pipe latch circuitry includes at least three pipe latches. ### Claim 11 (depends on 10) The system of claim 10, wherein the at least three pipe latches are parallel to each other. ### Claim 12 (depends on 10) The system of claim 10, wherein the pipe latch circuitry is configured to handle both the read command data and the write command data within one set of pipe latches. ### Claim 13 (depends on 9) The system of claim 9, wherein the pipe latch circuitry is within a bank area of the memory. ### Claim 14 (depends on 9) The system of claim 9, wherein the memory comprises dynamic random access memory (DRAM). ### Claim 15 (depends on 9) The system of claim 9, wherein the memory comprises ferroelectric random access memory (FeRAM). ### Claim 16 (depends on 13) The system of claim 13, wherein the memory comprises a plurality of banks. ### Claim 17 A method for accessing memory, the method comprising: receiving, at control circuitry, a memory access command to access multiple bits of electronic data stored in the memory; and responsive to receiving the memory access command to access the electronic data stored in the memory, providing, via the control circuitry, command data of the command to pipe latch circuitry and to error correction code (ECC) circuitry, wherein the pipe latch circuitry includes multiple parallel pipe latches in a bitslice area of the memory, wherein each respective bitslice area includes one or more circuit elements that are repeated for each bit associated with the memory access command, and wherein the multiple parallel pipe latches are configured to handle read command data and write command data for different sequential memory access operations transferred via a shared data path, and wherein the read command data comprises data read from the memory, and wherein the write command data comprises data to be written to the memory; receiving, at the pipe latch circuitry and from the control circuitry using a shared data path, the read command data or the write command data; operating the multiple parallel pipe latches in parallel to handle consecutive memory access commands with a fixed timing interval between commands; for write operations, latching the write command data in one or more of the parallel pipe latches of the pipe latch circuitry while the ECC circuitry determines an error correction code; for read operations, latching the read command data in one or more of the parallel pipe latches of the pipe latch circuitry while the ECC circuitry performs an error correction operation; and maintaining the read command data within the pipe latch circuitry for a period of time of a duration longer than error calculation time of the ECC circuitry. ### Claim 18 (depends on 17) The method of claim 17, wherein the memory access command to access memory comprises either a read command or a write command. ### Claim 19 (depends on 18) The method of claim 18, further comprising providing the read command data or the write command data to a same set of pipe latch circuitry for both a read command and a write command. ### Claim 20 (depends on 17) The method of claim 17, further comprising providing read data from the pipe latch circuitry to a global bus for further processing.