# US 12,603,121 B2 · Memory refresh with negative voltage generator

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- Number: US 12,603,121 B2
- Document ID: US12603121B2
- Status: Granted
- Kind: B2
- Application number: 18/451,988
- Filed: 2023-08-18
- Published: 2025-02-20
- Granted: 2026-04-14
- Earliest claimed: 2023-08-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Perng-Fei Yuh
- Web page: https://patentgrep.com/patent/US12603121B2

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4099: Dummy cell treatment; Reference voltage generators
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Limiting a leakage current of a memory device is provided. A sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. A reference current having a preset value is generated. The sensing current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.

## Claims

### Claim 1

A feedback circuit comprising:
a reference cell array connected to a memory device, wherein the reference cell array is operative to generate a sensing current that is representative of a leakage current of the memory device;
a reference current generator operative to generate a reference current having a preset value;
a comparator connected to the reference cell array and the reference current generator, wherein the comparator operative to compare the reference current with the sensing current and provide an enable signal based on the comparison; and
a negative voltage generator connected to the comparator, wherein the negative voltage generator operative to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to a plurality of word lines of the memory device in a standby mode.

### Claim 2 (depends on 1)

The feedback circuit of claim 1, wherein the bias voltage is also applied to a common word line of the reference cell array.

### Claim 3 (depends on 1)

The feedback circuit of claim 1, wherein the bias voltage is a negative voltage and decreases when the sensing current is greater than the reference current.

### Claim 4 (depends on 1)

The feedback circuit of claim 1, wherein the reference cell array comprises one or more reference cell sub-arrays placed at one or more locations on a die of the memory device.

### Claim 5 (depends on 1)

The feedback circuit of claim 1, wherein the sensing current is a summation of a drain-to-source currents of a plurality of reference cells of the reference cell array.

### Claim 6 (depends on 1)

The feedback circuit of claim 1, wherein a plurality of word lines of the reference cell array are connected together as one common word line, wherein a plurality of bit lines of the reference cell array are connected together as one common bit line, and wherein a plurality of source lines of the reference cell array are connected together as one common source line.

### Claim 7 (depends on 1)

The feedback circuit of claim 1, wherein the negative voltage generator is a charge pump.

### Claim 8

A memory device, comprising:
a memory cell array comprising a matrix of a plurality of rows and a plurality of columns, wherein each row of the plurality of rows comprises a first plurality of memory cells connected to a word line of a plurality of word lines, and wherein each column of the plurality of columns comprises a second plurality of memory cells connected to a bit line of a plurality of bit lines; and
a first feedback circuit operative to provide a bias voltage to the plurality of word lines of the memory cell array during a standby mode, wherein the feedback circuit comprises:
a reference cell array connected to the memory cell array, wherein the reference cell array generates a sensing current that is representative of a leakage current of the memory cell array device,
a comparator connected to the reference cell array, wherein the comparator compares a reference current with the sensing current and provides an enable signal based on the comparison, and
a negative voltage generator connected to the comparator, wherein the negative voltage generator generates a bias voltage based on the enable signal,
wherein the bias voltage is applied to the plurality of word lines of the memory cell array in a standby mode.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the first feedback circuit further comprises:
a reference current generator operative to generate the reference current having a preset value.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the negative voltage generator is a charge pump.

### Claim 11 (depends on 8)

The memory device of claim 8, wherein a plurality of word lines of the reference cell array are connected together as one common word line, wherein a plurality of bit lines of the reference cell array are connected together as one common bit line, and wherein a plurality of source lines of the reference cell array are connected together as one common source line.

### Claim 12 (depends on 8)

The memory device of claim 8, wherein the sensing current is a summation of a drain-to-source currents of a plurality of reference cells of the reference cell array.

### Claim 13 (depends on 8)

The memory device of claim 8, further comprising a second feedback circuit, wherein the second feedback circuit is operative to provide a pumped word line voltage to one of the plurality of word lines of the memory device for a read or a write operation.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the pumped word line voltage is relative to the bias voltage plus a set voltage level.

### Claim 15

A method of limiting a leakage current of a memory device, the method comprising:
generating, by a reference cell array connected to a memory cell array of the memory device, a sensing current that is a representative of a leakage current of the memory cell array of the memory device;
generating, by a reference current generator, a reference current having a preset value;
comparing, by a comparator connected to the reference cell array and the reference current generator, the sensing current with the reference current;
generating, by the comparator based on the comparison, an enable signal; and
adjusting, by a negative voltage generator connected to the comparator, a bias voltage applied to a plurality of word lines of the memory cell array based on the enable signal.

### Claim 16 (depends on 15)

The method of claim 15, wherein generating the sensing current comprises generating the sensing current through a reference cell array.

### Claim 17 (depends on 15)

The method of claim 15, wherein adjusting the bias voltage comprises decreasing the bias voltage in response to receiving the enable signal.

### Claim 18 (depends on 15)

The method of claim 15, wherein generating the enable signal comprises generating the enable signal when the sensing current is greater than the reference current.

### Claim 19 (depends on 15)

The method of claim 15, wherein adjusting the bias voltage applied to the plurality of word lines of the memory cell array based on the enable signal comprises decreasing the bias voltage in response to receiving the enable signal.

### Claim 20 (depends on 15)

The method of claim 15, wherein the bias voltage is a negative bias voltage.