Switch and hold biasing for memory cell imprint recovery

A host device, comprising:

• processing circuitry operable to couple with one or more memory devices using one or more channels, the processing circuitry configured to cause the host device to:
• transmit a command, to at least one of the one or more memory devices, to perform an imprint recovery procedure, wherein a recovery pulse of the imprint recovery procedure comprises:
• a first bias, with a first voltage magnitude having a voltage polarity, to a memory cell of the at least one of the one or more memory devices during a first duration of the recovery pulse;
• a bias reduction, between the first voltage magnitude and a second voltage magnitude having the voltage polarity, to the memory cell during a second duration of the recovery pulse after the first duration;
• and
• a second bias, with the second voltage magnitude having the voltage polarity, to the memory cell during a third duration of the recovery pulse after the second duration.

A method at a memory device, comprising:

• applying a recovery pulse to a memory cell of the memory device, wherein applying the recovery pulse comprises:
• biasing the memory cell, during a first duration of the recovery pulse, with a first voltage magnitude having a voltage polarity;
• reducing the biasing of the memory cell, during a second duration of the recovery pulse after the first duration, between the first voltage magnitude and a second voltage magnitude having the voltage polarity;
• and
• biasing the memory cell, during a third duration of the recovery pulse after the second duration, with the second voltage magnitude having the voltage polarity.