# US 12,603,116 B2 · Operating method of memory controller, and memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,116 B2 - Document ID: US12603116B2 - Status: Granted - Kind: B2 - Application number: 18/473,492 - Filed: 2023-09-25 - Published: 2024-04-25 - Granted: 2026-04-14 - Earliest claimed: 2022-10-25 - Assignees: Samsung Electronics Co., Ltd.; Seoul National University R&Db Foundation - Applicants: Samsung Electronics Co., Ltd.; Seoul National University R&DB Foundation - Inventors: Hoon Shin; Jaewook Lee; Donghwee Kim; Rihae Park - Web page: https://patentgrep.com/patent/US12603116B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 7/08: Control thereof - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device and an operating method of a memory controller are described in which the operating method includes determining that a NOT operation for data of a cell is to be performed by the memory device; forming, in a bit line connected to the cell, a reference voltage between a first voltage corresponding to the data and a second voltage corresponding to inversion data of the data; forming, in the bit line, a third voltage between the second voltage and the reference voltage by connecting the bit line and a bit line bar; forming the reference voltage in the bit line bar; and sensing the inversion data based on the third voltage formed in the bit line and the reference voltage formed in the bit line bar, wherein the inversion data comprises an output of the NOT operation for the data of the cell. ## Claims ### Claim 1 An operating method of a memory controller of a memory device, the operating method comprising: determining that a NOT operation for data of a cell is to be performed by the memory device; forming, in a bit line connected to the cell, a reference voltage between a first voltage corresponding to the data and a second voltage corresponding to inversion data of the data; forming, in the bit line, a third voltage between the second voltage and the reference voltage by connecting the bit line and a bit line bar; forming the reference voltage in the bit line bar; and sensing the inversion data based on the third voltage formed in the bit line and the reference voltage formed in the bit line bar, wherein the inversion data comprises an output of the NOT operation for the data of the cell. ### Claim 2 (depends on 1) The operating method of claim 1, wherein sensing the data comprises forming the first voltage corresponding to the data in the bit line and forming the second voltage corresponding to an inversion voltage of the first voltage in the bit line bar. ### Claim 3 (depends on 1) The operating method of claim 1, wherein sensing of the inversion data comprises sensing the inversion data using a sense amplifier. ### Claim 4 (depends on 1) The operating method claim 1, wherein a first signal controlling a transistor for pre-charging the bit line is transmitted independently from a second signal for pre-charging the bit line bar. ### Claim 5 (depends on 1) The operating method of claim 1, wherein forming the reference voltage comprises pre-charging the bit line by reducing an initial voltage of the bit line to the reference voltage or increasing the initial voltage of the bit line to the reference voltage. ### Claim 6 (depends on 1) The operating method of claim 1, wherein connecting the bit line and the bit line bar comprises operating a transistor in a node connecting the bit line to the bit line bar. ### Claim 7 (depends on 1) The operating method of claim 1, wherein sensing the inversion data comprises is based on a difference between the reference voltage and the third voltage formed in the bit line. ### Claim 8 (depends on 1) A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1. ### Claim 9 An operating method of a memory controller of a memory device, the operating method comprising: determining that a logical operation is to be performed on a first cell and a second cell by the memory device, wherein the logical operation comprises an AND operation or an OR operation; copying data of the first cell, the second cell, and a third cell into a fourth cell, a fifth cell, and a sixth cell, respectively; and sensing an output value of the logical operation based on a voltage formed in a bit line connected to the first cell and to the sixth cell. ### Claim 10 (depends on 9) The operating method of claim 9, further comprising: setting a value of the third cell based on whether the logical operation comprises the AND operation or the OR operation. ### Claim 11 (depends on 9) The operating method of claim 9, further comprising: simultaneously activating wordlines of the first cell to the sixth cell, respectively; and sensing, using a sense amplifier, a change in a voltage with respect to a bit line connected to the wordlines. ### Claim 12 A memory device comprising: a plurality of wordlines; a bit line connected to at least one activated wordline among the plurality of wordlines; a bit line bar configured to transfer inversion data of the bit line; a sense amplifier configured to sense data of the bit line and data of the bit line bar; and a pre-charge unit configured to pre-charge the bit line and the bit line bar, wherein the pre-charge unit is configured to form a reference voltage between a first voltage corresponding to data of a cell and a second voltage corresponding to the inversion data of the data of the cell by pre-charging the bit line, wherein the memory device is configured to form, in the bit line, a third voltage between the second voltage and the reference voltage by connecting the bit line and the bit line bar, and wherein the memory device is configured to perform a NOT operation based on the inversion data. ### Claim 13 (depends on 12) The memory device of claim 12, wherein the memory device is configured to form the reference voltage in the bit line bar after forming the third voltage. ### Claim 14 (depends on 12) The memory device of claim 12, wherein the sense amplifier is configured to sense the inversion data of the data of the cell by amplifying a difference between the third voltage formed in the bit line and the reference voltage. ### Claim 15 A method comprising: storing data in a first cell connected to a sense amplifier via a bit line of the first cell; storing inversion data in a second cell connected to the sense amplifier via a bit line bar of the first cell; determining that a NOT operation is to be performed on the data of the first cell; forming a voltage in the bit line based on the inversion data; and performing the NOT operation by sensing the voltage in the bit line using the sense amplifier. ### Claim 16 (depends on 15) The method of claim 15, further comprising: forming a reference voltage in the bit line; connecting the bit line and the bit line bar to form the voltage in the bit line; and forming the reference voltage in the bit line bar; and detecting a voltage difference between the bit line and the bit line bar, wherein the NOT operation is performed based on the voltage difference. ### Claim 17 (depends on 15) The method of claim 15, wherein the first cell and the second cell comprise dynamic random access memory (DRAM) memory cells. ### Claim 18 (depends on 15) The method of claim 15, wherein the first cell and the second cell are arranged according to an open bit line architecture, and wherein the first cell is located in a different subarray than the second cell.