# US 12,603,115 B2 · Method and apparatus to perform training on a data bus between a dynamic random access memory (DRAM) and a data buffer on a buffered dual in-line memory module

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- Number: US 12,603,115 B2
- Document ID: US12603115B2
- Status: Granted
- Kind: B2
- Application number: 17/950,663
- Filed: 2022-09-22
- Published: 2023-01-19
- Granted: 2026-04-14
- Earliest claimed: 2022-09-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Saravanan Sethuraman; Tonia M. Rose; George Vergis; John V. Lovelace
- Web page: https://patentgrep.com/patent/US12603115B2

## CPC

- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/50012: {of timing}
- G11C 7/225: {Clock input buffers}
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

## Claims

### Claim 1

A memory module comprising:
a memory integrated circuit including a data bus having memory module data (MDQ) signal lines and memory module data strobe (MDQS) signal lines;
a Registering Clock Driver (RCD) including a command bus interface to a host memory controller and a memory module command bus (QCA) interface to the memory integrated circuit, the RCD to trigger training of the MDQ signal lines and the MDQS signal lines; and
a data buffer coupled to the MDQ signal lines and the MDQS signal lines, the data buffer including a hardware state machine to perform training of the MDQS signal lines and the MDQ signal lines in response to a training request received from the RCD.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the training request is MDQS Receive Enable (MRE) training.

### Claim 3 (depends on 1)

The memory module of claim 1, wherein the training request is MDQS Read Delay (MRD) training.

### Claim 4 (depends on 1)

The memory module of claim 1, wherein the training is performed prior to enabling normal operation of the memory integrated circuit.

### Claim 5 (depends on 1)

The memory module of claim 1, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Load Reduced Double Data Rate Dual In-Line Memory Module (LR-DIMM).

### Claim 6 (depends on 1)

The memory module of claim 1, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Multiplexed Rank Dual In-Line Memory Module (MR-DIMM).

### Claim 7

A system comprising:
a memory controller; and
a memory module comprising:
a memory integrated circuit including a data bus having memory module data (MDQ) signal lines and memory module data strobe (MDQS) signal lines;
a Registering Clock Driver (RCD) including a command bus interface to a host memory controller and a memory module command bus (QCA) interface to the memory integrated circuit, the RCD to trigger training of the MDQ signal lines and the MDQS signal lines; and
a data buffer coupled to the MDQ signal lines and the MDQS signal lines, the data buffer including a hardware state machine to perform training of the MDQS signal lines and the MDQ signal lines in response to a training request received from the RCD.

### Claim 8 (depends on 7)

The system of claim 7, wherein the training request is MDQS Receive Enable (MRE) training.

### Claim 9 (depends on 7)

The system of claim 7, wherein the training request is MDQS Read Delay (MRD) training.

### Claim 10 (depends on 7)

The system of claim 7, wherein the training is performed prior to enabling normal operation of the memory integrated circuit.

### Claim 11 (depends on 7)

The system of claim 7, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Load Reduced Double Data Rate Dual In-Line Memory Module (LR-DIMM).

### Claim 12 (depends on 7)

The system of claim 7, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Multiplexed Rank Dual In-Line Memory Module (MR-DIMM).

### Claim 13 (depends on 7)

The system of claim 7, further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor; or
a battery to power the system.

### Claim 14

A method, to perform training of a data bus in a memory module, comprising:
triggering training of memory module data (MDQ) signal lines and memory module data strobe (MDQS) signal lines, by a Registering Clock Driver (RCD), the RCD including a command bus interface to a host memory controller and a memory module command bus (QCA) interface to a memory integrated circuit, the memory integrated circuit including a data bus having the MDQ signal lines and the MDQS signal lines; and
performing training of the MDQS signal lines and the MDQ signal lines, by a hardware state machine in a data buffer coupled to the MDQ signal lines and the MDQS signal lines, in response to a training request received from the RCD.

### Claim 15 (depends on 14)

The method of claim 14, wherein the training request is MDQS Receive Enable (MRE) training.

### Claim 16 (depends on 14)

The method of claim 14, wherein the training request is MDQS Read Delay (MRD) training.

### Claim 17 (depends on 14)

The method of claim 14, wherein the training is performed prior to enabling normal operation of the memory integrated circuit.

### Claim 18 (depends on 14)

The method of claim 14, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Load Reduced Double Data Rate Dual In-Line Memory Module (LR-DIMM).

### Claim 19 (depends on 14)

The method of claim 14, wherein the memory integrated circuit is a Dynamic Random Access Memory (DRAM) and the memory module is a Multiplexed Rank Dual In-Line Memory Module (MR-DIMM).