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US 12,603,114 B2Granted
Memory device
AssigneeKioxia Corporation
InventorTakeshi Sugimoto
Life of this patent
Estimating the term…
Abstract
A memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.
Claims14
A memory device, comprising:
- a plurality of memory cells provided for each of a plurality of layers arranged in a first direction, the memory cells of each of the layers including a plurality of groups of memory cells, the memory cells of each of the groups being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions;
- a plurality of first wirings arranged in the third direction in each of the layers and respectively connected to the groups of memory cells in each of the layers;
- a plurality of first transistors each connected to a corresponding one of the first wirings;
- a plurality of second wirings each connected to the first transistors of a corresponding one of the layers;
- a plurality of third wirings each extending in the first direction and connected to one of the memory cells in each of the layers;
- and
- a plurality of fourth wirings each extending in the first direction and connected to a gate of a corresponding one of the first transistors in each of the layers, wherein
- each of the memory cells includes:
- a second transistor having one end connected to the corresponding first wiring and a gate connected to the corresponding third wiring, and
- a capacitor having one electrode connected to another end of the second transistor.
7 more elements
A memory device, comprising:
- a plurality of memory cells provided for each of a plurality of layers arranged in a first direction, the memory cells of each of the layers including a plurality of groups of memory cells, the memory cells of each of the groups being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions;
- a plurality of first wirings arranged in the third direction in each of the layers and respectively connected to the groups of memory cells in each of the layers;
- a plurality of first transistors each connected to a corresponding one of the first wirings;
- a plurality of second wirings each connected to the first transistors of a corresponding one of the layers;
- a plurality of third wirings each extending in the first direction and connected to one of the memory cells in each of the layers;
- a plurality of fourth wirings each extending in the first direction and connected to a gate of a corresponding one of the first transistors in each of the layers;
- and
- a plurality of sense amplifiers each connected to a corresponding one of the second wirings, wherein
- the sense amplifiers include a plurality of first sense amplifiers in a first region and a plurality of second sense amplifiers in a second region,
- the memory cells are between the first and second regions, and
- each of the first sense amplifiers is connected to the corresponding second wiring of an odd-numbered layer among the layers, and each of the second sense amplifiers is connected to the corresponding second wiring of an even-numbered layer among the layers.
8 more elements
A memory device, comprising:
- a plurality of memory cells provided for each of a plurality of layers arranged in a first direction, the memory cells of each of the layers including a plurality of groups of memory cells, the memory cells of each of the groups being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions;
- a plurality of first wirings arranged in the third direction in each of the layers and respectively connected to the groups of memory cells in each of the layers;
- a plurality of first transistors each connected to a corresponding one of the first wirings;
- a plurality of second wirings each connected to the first transistors of a corresponding one of the layers;
- a plurality of third wirings each extending in the first direction and connected to one of the memory cells in each of the layers;
- a plurality of fourth wirings each extending in the first direction and connected to a gate of a corresponding one of the first transistors in each of the layers;
- a plurality of first sense amplifiers;
- and
- a plurality of second sense amplifiers, wherein
- each of the second wirings includes fifth and sixth wirings separated from each other, and
- each of the first sense amplifiers is connected to the fifth wiring of one of the second wirings, and each of the second sense amplifiers is connected to the sixth wiring of said one of the second wirings.
8 more elements
Dependencies are inferred from the claim text.