Circuit and method for video data conversion and display device

A video data conversion circuit, comprising:

• a pixel splicing circuit, configured to sequentially receive each group of pixel data in each frame of image data in input video data, to perform pixel splicing on the received pixel data, and to output spliced pixel data;
• and
• a data conversion circuit, configured to perform data processing on the spliced pixel data to convert each frame of image data into first image data representing a first part of a corresponding frame of image and second image data representing a second part of the corresponding frame of image, the first image data and the second image data being configured for driving a display panel to complete display of the corresponding frame of image,
• wherein the first part at least comprises a left half part of the corresponding frame of image, and the second part at least comprises a right half part of the corresponding frame of image,
• wherein a data synthesis processing is performed on the first image data and the second image data by a subsequent-stage circuit of the video data conversion circuit, and the data synthesis processing includes a filtering process achieved by a multi-stage filter,
• wherein the first part and the second part have an overlap region, a width of the overlap region expressed in number of pixel is at least greater than one-half of the number of stages of the multi-stage filter,
• wherein the data conversion circuit comprises:
• a first static memory, configured to write the received spliced pixel data according to a first write address sequence when receiving a first write enable signal being valid, so as to store the first image data corresponding to each frame of image data, and to output the stored first image data according to a first read address sequence when receiving a first read enable signal being valid;
• a second static memory, configured to write the received spliced pixel data according to a second write address sequence when receiving a second write enable signal being valid, so as to store the second image data corresponding to each frame of image data, and to output the stored second image data according to a second read address sequence when receiving a second read enable signal being valid;
• a first write controller, configured to output the first write enable signal being valid when receiving a row enable signal, and to output the first write enable signal being invalid when receiving a second flag signal;
• a first read controller, configured to output the first read enable signal being valid when receiving a first flag signal;
• a second write controller, configured to output the second write enable signal being valid when receiving the first flag signal, and to output the second write enable signal being invalid when receiving a third flag signal;
• a second read controller, configured to output the second read enable signal being valid when receiving the first flag signal;
• and
• a flag signal generating unit, configured to generate the first flag signal, the second flag signal, and the third flag signal according to a row resolution of the display panel, the row enable signal, and a size of an image overlap region, wherein the image overlap region is the overlap region of the first part and the second part.