# US 12,603,052 B2 · Pixel circuit and electroluminescent display apparatus including the same

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- Number: US 12,603,052 B2
- Document ID: US12603052B2
- Status: Granted
- Kind: B2
- Application number: 18/982,886
- Filed: 2024-12-16
- Published: 2025-08-28
- Granted: 2026-04-14
- Earliest claimed: 2024-02-22
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Yong Hyeon Shin; Jai Youn Song; Jin U Lee
- Web page: https://patentgrep.com/patent/US12603052B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 2300/0804: Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0252: Improving the response speed
- G09G 2340/16: Determination of a pixel data signal depending on the signal applied in the previous frame
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A pixel circuit and an electroluminescent display apparatus are discussed. The pixel circuit can include a driving transistor having a gate electrode connected to a gate node and a source electrode connected to a source node, and configured to generate a driving current. The pixel circuit can further include a first light emitting device having a first anode electrode, a second light emitting device having a second anode electrode, a first emission transistor connecting the source node to the first anode electrode in an odd frame and disconnecting the source node from the first anode electrode during an even frame in response to a first emission signal, and a second emission transistor connecting the source node to the second anode electrode in the even frame and disconnecting the source node from the second anode electrode during the odd frame in response to a second emission signal.

## Claims

### Claim 1

A pixel circuit comprising:
a driving transistor including a gate electrode connected to a gate node and a source electrode connected to a source node, and configured to generate a driving current;
a first light emitting device including a first anode electrode and configured to emit light in response to the driving current;
a second light emitting device including a second anode electrode and configured to emit light in response to the driving current;
a first emission transistor configured to connect the source node to the first anode electrode in an odd frame and disconnect the source node from the first anode electrode during an even frame, in response to a first emission signal;
a second emission transistor configured to connect the source node to the second anode electrode in the even frame and disconnect the source node from the second anode electrode during the odd frame, in response to a second emission signal;
a first scan transistor configured to supply a reset voltage to the first anode electrode based on a first scan signal; and
a second scan transistor configured to supply the reset voltage to the second anode electrode based on a second scan signal,
wherein the first light emitting device is turned on during an emission period of the odd frame and maintains an off state during the even frame, and the second light emitting device is turned on during an emission period of the even frame and maintains an off state during the odd frame, and
wherein the first scan transistor is turned on in another period, except the emission period, of the odd frame and is turned on in all periods of the even frame, and the second scan transistor is turned on in another period, except the emission period, of the even frame and is turned on in all periods of the odd frame.

### Claim 2 (depends on 1)

The pixel circuit of claim 1, wherein the first emission transistor is turned on during the emission period of the odd frame and is turned off during all periods of the even frame, and
wherein the second emission transistor is turned on during the emission period of the even frame and is turned off during all periods of the odd frame.

### Claim 3 (depends on 1)

The pixel circuit of claim 1, wherein, in a data writing period preceding the emission period of the odd frame or a data writing period preceding the emission period of the even frame, a data voltage included in a predetermined voltage range is applied to the gate node so as to implement a gray level, and
wherein the reset voltage is less than a lower limit voltage value of the predetermined voltage range.

### Claim 4

An electroluminescent display apparatus comprising:
a display panel including a plurality of pixels;
a gate driver configured to drive scan lines and emission lines connected to the plurality of pixels; and
a data driver configured to drive data lines connected to the plurality of pixels,
wherein a pixel circuit of each of the plurality of pixels comprises:
a driving transistor including a gate electrode connected to a gate node and a source electrode connected to a source node, and configured to generate a driving current;
a first light emitting device including a first anode electrode, and configured to emit light in response to the driving current;
a second light emitting device including a second anode electrode, and configured to emit light in response to the driving current;
a first emission transistor configured to connect the source node to the first anode electrode in an odd frame and disconnect the source node from the first anode electrode during an even frame, in response to a first emission signal supplied through a first emission line;
a second emission transistor configured to connect the source node to the second anode electrode in the even frame and disconnect the source node from the second anode electrode during the odd frame, in response to a second emission signal supplied through a second emission line;
a first scan transistor configured to supply a reset voltage to the first anode electrode, based on a first scan signal supplied through a first scan line; and
a second scan transistor configured to supply the reset voltage to the second anode electrode, based on a second scan signal supplied through a second scan line,
wherein the first light emitting device is turned on during an emission period of the odd frame and maintains an off state during the even frame, and the second light emitting device is turned on during an emission period of the even frame and maintains an off state during the odd frame, and
wherein the first scan transistor is turned on in another period, except the emission period, of the odd frame and is turned on in all periods of the even frame, and the second scan transistor is turned on in another period, except the emission period, of the even frame and is turned on in all periods of the odd frame.

### Claim 5 (depends on 4)

The electroluminescent display apparatus of claim 4, wherein the first emission transistor is turned on during the emission period of the odd frame and is turned off during all periods of the even frame, and
wherein the second emission transistor is turned on during the emission period of the even frame and is turned off during all periods of the odd frame.

### Claim 6 (depends on 4)

The electroluminescent display apparatus of claim 4, wherein, in a data writing period preceding the emission period of the odd frame or a data writing period preceding the emission period of the even frame, a data voltage included in a predetermined voltage range is applied to the gate node so as to implement a gray level, and
wherein the reset voltage is less than a lower limit voltage value of the predetermined voltage range.

### Claim 7 (depends on 4)

The electroluminescent display apparatus of claim 4, wherein the pixel circuit is configured to:
supply a reset voltage to the first and second anode electrodes in a period before the emission period of the odd frame during the odd frame, and
supply the reset voltage to the first and second anode electrodes in a period before the emission period of the even frame during the even frame.