# US 12,603,044 B2 · Pixel circuit and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,044 B2 - Document ID: US12603044B2 - Status: Granted - Kind: B2 - Application number: 18/676,614 - Filed: 2024-05-29 - Published: 2025-02-20 - Granted: 2026-04-14 - Earliest claimed: 2023-08-14 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., LTD. - Inventors: Jinjoo Ha; Sehyun Lee; Kwihyun Kim - Web page: https://patentgrep.com/patent/US12603044B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel circuit comprises a light-emitting element, a first transistor which provides a driving current to the light-emitting element, a first capacitor including a first terminal connected to a first terminal of the first transistor and a second terminal connected to a gate terminal of the first transistor, a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to a second terminal of the first transistor, a second transistor which provides a data voltage to the gate terminal of the first transistor in response to a write gate signal, and a third transistor which connects the second terminal of the first transistor and an anode terminal of the light-emitting element in response to a first emission signal. ## Claims ### Claim 1 A pixel circuit comprising: a light-emitting element including an anode terminal; a first transistor which provides a driving current to the light-emitting element, the first transistor including a gate terminal, a first terminal and a second terminal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor which provides a data voltage to the gate terminal of the first transistor in response to a write gate signal; a third transistor which connects the second terminal of the first transistor and the anode terminal of the light-emitting element in response to a first emission signal; a fourth transistor which provides a first power supply voltage to the first terminal of the first transistor in response to a second emission signal; and a fifth transistor provides a bias voltage to the anode terminal of the light-emitting element in response to an initialization gate signal, wherein the gate terminal of the first transistor is connected to a first node, the first terminal of the first transistor is connected to a second node, and the second terminal of the first transistor is connected to a third node, the first terminal of the first capacitor is connected to the second node and the second terminal of the first capacitor is connected to the first node, the first terminal of the second capacitor is connected to the first node and the second terminal of the second capacitor is connected to the third node, the second transistor includes a gate terminal which receives the write gate signal, a first terminal connected to a data line, and a second terminal connected to the first node, the third transistor includes a gate terminal which receives the first emission signal, a first terminal connected to the third node, and a second terminal connected to the anode terminal of the light-emitting element, the fourth transistor includes a gate terminal which receives the second emission signal, a first terminal connected to a line of the first power supply voltage, and a second terminal connected to the second node, the fifth transistor includes a gate terminal which receives the initialization gate signal, a first terminal connected to the third node, and a second terminal connected to a line of the bias voltage, and the anode terminal of the light-emitting element is connected to the second terminal of the third transistor, and the light-emitting element further includes a cathode terminal connected to a line of a second power supply voltage. ### Claim 2 (depends on 1) The pixel circuit of claim 1, wherein, in a first period, the second emission signal, the write gate signal, and the initialization gate signal have an active level, and the first emission signal has an inactive level. ### Claim 3 (depends on 2) The pixel circuit of claim 2, wherein, in a second period after the first period, the write gate signal and the initialization gate signal have the active level, and the first emission signal and the second emission signal have the inactive level. ### Claim 4 (depends on 3) The pixel circuit of claim 3, wherein, in a third period after the second period, the second emission signal, the write gate signal, and the initialization gate signal have the active level, and the first emission signal has the inactive level. ### Claim 5 (depends on 4) The pixel circuit of claim 4, wherein, in a fourth period after the third period, the first emission signal and the second emission signal have the active level, and the write gate signal and the initialization gate signal have the inactive level. ### Claim 6 (depends on 5) The pixel circuit of claim 5, wherein, in the fourth period, a voltage of the gate terminal of the first transistor is divided by the first capacitor and the second capacitor. ### Claim 7 (depends on 5) The pixel circuit of claim 5, wherein, in the fourth period, the third transistor is turned on so that the third transistor connects the second terminal of the first transistor and the anode terminal of the light-emitting element. ### Claim 8 (depends on 4) The pixel circuit of claim 4, wherein, in the third period, the first capacitor maintains a threshold voltage of the first transistor. ### Claim 9 (depends on 4) The pixel circuit of claim 4, wherein, in the first to third periods, the third transistor is turned off so that the second terminal of the first transistor and the anode terminal of the light-emitting element are not connected to each other. ### Claim 10 (depends on 3) The pixel circuit of claim 3, wherein, in the second period, when the fourth transistor is turned off, the first capacitor stores a threshold voltage of the first transistor. ### Claim 11 (depends on 2) The pixel circuit of claim 2, wherein, in the first period, the second transistor provides the data voltage to the gate terminal of the first transistor, the first terminal of the first transistor is initialized to the first power supply voltage, and the second terminal of the first transistor is initialized with the bias voltage. ### Claim 12 (depends on 1) The pixel circuit of claim 1, wherein a back gate terminal of the first transistor is connected to the first terminal of the first transistor. ### Claim 13 (depends on 1) The pixel circuit of claim 1, wherein back gate terminals of the first to fifth transistors receive the first power supply voltage. ### Claim 14 (depends on 1) The pixel circuit of claim 1, wherein the first to fifth transistors are P-type transistors. ### Claim 15 An electronic device comprising: a display device comprising: a display panel including a pixel circuit, the pixel circuit including: a light-emitting element including an anode terminal; a first transistor which provides a driving current to the light-emitting element, the first transistor including a gate terminal, a first terminal and a second terminal; a first capacitor including a first terminal connected to the first terminal of the first transistor and a second terminal connected to the gate terminal of the first transistor; a second capacitor including a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the second terminal of the first transistor; a second transistor which provides a data voltage to the gate terminal of the first transistor in response to a write gate signal; a third transistor which connects the second terminal of the first transistor and the anode terminal of the light-emitting element in response to a first emission signal; a fourth transistor which provides a first power supply voltage to the first terminal of the first transistor in response to a second emission signal; and a fifth transistor provides a bias voltage to the anode terminal of the light-emitting element in response to an initialization gate signal a data driver which provides the data voltage to the pixel circuit; a gate driver which provides the write gate signal to the pixel circuit; an emission driver which provides the first emission signal to the pixel circuit; and a driving controller which controls the data driver, the gate driver, and the emission driver, wherein the gate terminal of the first transistor is connected to a first node, the first terminal of the first transistor is connected to a second node, and the second terminal of the first transistor is connected to a third node, the first terminal of the first capacitor is connected to the second node and the second terminal of the first capacitor is connected to the first node, the first terminal of the second capacitor is connected to the first node and the second terminal of the second capacitor is connected to the third node, the second transistor includes a gate terminal which receives the write gate signal, a first terminal connected to a data line, and a second terminal connected to the first node, the third transistor includes a gate terminal which receives the first emission signal, a first terminal connected to the third node, and a second terminal connected to the anode terminal of the light-emitting element, the fourth transistor includes a gate terminal which receives the second emission signal, a first terminal connected to a line of the first power supply voltage, and a second terminal connected to the second node, the fifth transistor includes a gate terminal which receives the initialization gate signal, a first terminal connected to the third node, and a second terminal connected to a line of the bias voltage, and the anode terminal of the light-emitting element is connected to the second terminal of the third transistor, and the light-emitting element further includes a cathode terminal connected to a line of a second power supply voltage. ### Claim 16 (depends on 15) The electronic display device of claim 15, wherein, the emission driver further provides a second emission signal to the pixel circuit, and the pixel circuit further includes a fourth transistor which provides a first power supply voltage to the first terminal of the first transistor in response to the second emission signal. ### Claim 17 (depends on 16) The electronic device of claim 16, wherein, the gate driver further provides an initialization gate signal to the pixel circuit, and the pixel circuit further includes a fifth transistor which provides a bias voltage to the anode terminal of the light-emitting element in response to the initialization gate signal.