# US 12,603,035 B2 · Display apparatus and driving method thereof

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- Number: US 12,603,035 B2
- Document ID: US12603035B2
- Status: Granted
- Kind: B2
- Application number: 19/066,445
- Filed: 2025-02-28
- Published: 2025-08-28
- Granted: 2026-04-14
- Earliest claimed: 2024-02-28
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Jong Taek Kim; Ji Yong Hwang; Ki Tae Yu
- Web page: https://patentgrep.com/patent/US12603035B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G06F 3/0412: {Digitisers structurally integrated in a display}
- G06F 3/04164: {Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads}
- G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED]
- G06F 3/044: by capacitive means
- G06F 3/0443: {using a single layer of sensing electrodes}
- G06F 2203/04103: Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
- G09G 3/035: {for flexible display surfaces}
- G09G 3/3225: using an active matrix
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2320/0693: Calibration of display systems
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A display apparatus can include a display panel configured to display an image, a gate driver configured to apply a gate signal to the display panel, a driving circuit, and a jitter correction circuit. The driving circuit includes a signal generating circuit configured to generate a clock signal for driving the gate driver, and a frequency generating circuit configured to generate an internal oscillator signal to allow the clock signal to be generated with an internally set frequency band. The jitter correction circuit can correct a jitter of the clock signal, based on the internal oscillator signal and the clock signal fed back from the signal generating circuit.

## Claims

### Claim 1

A display apparatus comprising:
a display panel configured to display an image;
a gate driver configured to apply a gate signal to the display panel;
a driving circuit including a signal generating circuit configured to generate a clock signal for driving the gate driver and a frequency generating circuit configured to generate an internal oscillator signal to allow the clock signal to be generated with an internally set frequency band; and
a jitter correction circuit configured to correct a jitter of the clock signal, based on the internal oscillator signal and the clock signal fed back from the signal generating circuit,
wherein the jitter correction circuit is configured to correct the jitter of the clock signal, and
wherein the jitter correction circuit comprises:
a jitter detection circuit configured to detect the jitter of the clock signal;
a jitter selection circuit configured to generate a jitter selection value based on the jitter of the clock signal;
a jitter integral circuit configured to accumulate and integrate the jitter selection value to generate an integral jitter value; and
a jitter comparison circuit configured to compare the integral jitter value with the internal oscillator signal.

### Claim 2 (depends on 1)

The display apparatus of claim 1, wherein the jitter detection circuit comprises:
an XOR (Exclusive OR) gate configured to perform an XOR operation on the clock signal and a division value obtained by dividing the internal oscillator signal to provide an output value;
a first AND gate configured to perform an AND operation on the output value of the XOR gate and the division value obtained by dividing the internal oscillator signal to output a first AND operation value; and
a second AND gate configured to perform an AND operation on the output value of the XOR gate and an inversion value obtained by inverting the division value to output a second AND operation value.

### Claim 3 (depends on 2)

The display apparatus of claim 2, wherein the jitter selection circuit outputs the jitter selection value defining whether the jitter of the clock signal is + jitter or − jitter, based on the first AND operation value and the second AND operation value.

### Claim 4 (depends on 1)

The display apparatus of claim 1, wherein the jitter correction circuit comprises:
a signal division circuit configured to output a division value obtained by dividing the internal oscillator signal; and
a signal count circuit configured to count the division value of the internal oscillator signal output from the signal division circuit to output a count value,
wherein the jitter comparison circuit is configured to compare the internal oscillator signal with the count value output from the signal count circuit and generate a jitter correction value, based on a comparison result.

### Claim 5 (depends on 4)

The display apparatus of claim 4, wherein the jitter correction circuit comprises a jitter margin control circuit configured to generate a jitter margin control value for correcting a jitter according to whether there is a jitter or not and an intensity of the jitter, based on the jitter correction value output from the jitter correction circuit.

### Claim 6 (depends on 1)

The display apparatus of claim 1, wherein the jitter correction circuit is included in the driving circuit.

### Claim 7 (depends on 1)

A driving method of the display apparatus of claim 1, the driving method comprising:
detecting the jitter of the clock signal for driving the gate driver;
generating the jitter selection value based on the jitter of the clock signal;
accumulating and integrating the jitter selection value to generate the integral jitter value; and
comparing the integral jitter value with the internal oscillator signal to generate a comparison result, and generating a jitter correction value for correcting the jitter of the clock signal, based on the comparison result.

### Claim 8

A display apparatus comprising:
a display panel configured to display an image;
a gate driver configured to apply a gate signal to the display panel;
a driving circuit including a signal generating circuit configured to generate a clock signal for driving the gate driver and a frequency generating circuit configured to generate an internal oscillator signal to allow the clock signal to be generated with an internally set frequency band; and
a jitter correction circuit configured to correct a jitter of the clock signal, based on the internal oscillator signal and the clock signal fed back from the signal generating circuit,
wherein the jitter correction circuit comprises:
a signal division circuit configured to output a division value obtained by dividing the internal oscillator signal;
a signal count circuit configured to count the division value of the internal oscillator signal output from the signal division circuit to output a count value; and
a jitter comparison circuit configured to compare the internal oscillator signal with the count value output from the signal count circuit and generate a jitter correction value, based on a comparison result.