# US 12,603,034 B2 · CMOS circuit

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- Number: US 12,603,034 B2
- Document ID: US12603034B2
- Status: Granted
- Kind: B2
- Application number: 18/477,555
- Filed: 2023-09-29
- Published: 2024-04-04
- Granted: 2026-04-14
- Earliest claimed: 2022-09-29
- Assignees: Magnolia White Corporation
- Applicants: Magnolia White Corporation
- Inventors: Kenji Harada
- Web page: https://patentgrep.com/patent/US12603034B2

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

According to one embodiment, a CMOS circuit includes a p-channel type transistor including a polycrystalline silicon layer and an n-channel type transistor including an oxide semiconductor layer, and the p-channel transistor and the n-channel transistor are complementarily connected to each other, and the polycrystalline silicon layer and the oxide semiconductor layer overlap each other in plan view.

## Claims

### Claim 1

A CMOS circuit comprising:
a p-channel type transistor including a polycrystalline silicon layer; and
an n-channel type transistor including an oxide semiconductor layer, wherein
the p-channel transistor and the n-channel transistor are complementarily connected to each other,
the polycrystalline silicon layer and the oxide semiconductor layer overlap each other in plan view,
the CMOS circuit is an inverter comprising one of the p-channel type transistor and one of the n-channel type transistor,
a first drain electrode of the p-channel transistor is connected to the polycrystalline silicon layer,
a second drain electrode of the n-channel transistor is connected to the oxide semiconductor layer and the first drain electrode, and
a gate electrode of the p-channel transistor and a gate electrode of the n-channel transistor overlap each other in plan view.

### Claim 2 (depends on 1)

The CMOS circuit according to claim 1, wherein the polycrystalline silicon layer of the p-channel transistor contains an impurity which impart a p-type.

### Claim 3

A CMOS comprising:
a p-channel type transistor including a polycrystalline silicon layer; and
an n-channel type transistor including an oxide semiconductor layer, wherein
the p-channel transistor and the n-channel transistor are complementarily connected to each other,
the polycrystalline silicon layer and the oxide semiconductor layer overlap each other in plan view,
the CMOS circuit is an inverter comprising one of the p-channel type transistor and one of the n-channel type transistor,
a drain electrode of the n-channel transistor is connected to the oxide semiconductor layer and the polycrystalline silicon layer, and
a gate electrode of the p-channel transistor and a gate electrode of the n-channel transistor overlap each other in plan view.

### Claim 4 (depends on 3)

The CMOS circuit according to claim 3, wherein the polycrystalline silicon layer of the p-channel transistor contains an impurity which imparts a p-type.