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US 12,603,031 B2Granted
Display device and controller
AssigneeLG Display Co., Ltd.
InventorsBeomjun Shin, Gyeongho Ryu
Life of this patent
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Abstract
A display device can include a display panel having a plurality of subpixels, a memory storing image control data for controlling an image displayed on the display panel, a mode control signal generation circuit generating a mode control signal based on a first mode signal supplied from a first controller, and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.
Claims21
A display device, comprising:
- a display panel configured to display an image;
- a memory configured to store image control data for controlling the image displayed on the display panel, the memory including a plurality of chips;
- a mode control signal generation circuit configured to generate a mode control signal based on a first mode signal supplied from a first controller;
- and
- a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal,
- wherein the first controller includes a master buffer configured to transfer an external control signal to the memory,
- wherein the display device further comprises a slave buffer configured to transfer an internal control signal to the memory, the slave buffer being positioned inside the second controller or on a control printed circuit board outside the second controller, and
- wherein the master buffer and the slave buffer are controlled by the mode control signal.
5 more elements
A timing controller, comprising:
- a first edge detection circuit configured to generate a mode enable edge signal by detecting an edge where a mode enable signal supplied from a host controller is turned on;
- a second edge detection circuit configured to generate a chip selection edge signal by detecting an edge where a chip selection signal supplied from the host controller is turned off;
- a first logic gate configured to generate a mode control signal for determining a control authority of the host controller for a memory using the mode enable edge signal and the chip selection edge signal;
- and
- a second logic gate configured to generate a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit using the mode enable edge signal and the chip selection edge signal,
- wherein the timing controller shares the memory with the host controller.
3 more elements
Dependencies are inferred from the claim text.