# US 12,603,029 B2 · Power management circuit and timing controller for display device

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- Number: US 12,603,029 B2
- Document ID: US12603029B2
- Status: Granted
- Kind: B2
- Application number: 18/650,326
- Filed: 2024-04-30
- Published: 2024-08-22
- Granted: 2026-04-14
- Earliest claimed: 2020-12-18
- Assignees: Lx Semicon Co., Ltd.
- Applicants: Lx Semicon Co., Ltd.
- Inventors: Yang Sun
- Web page: https://patentgrep.com/patent/US12603029B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G06F 1/3265: {Power saving in display device}
- G06F 1/3287: by switching off individual functional units in the computer system
- G09G 3/3611: {Control of matrices with row and column drivers}
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/021: Power management, e.g. power saving
- G09G 2360/16: Calculation or use of calculated indices related to luminance levels in display data
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present embodiment relates to a power management circuit and timing controller for a display device. The power management circuit optimizes power consumption by receiving analysis information from a timing controller capable of analyzing image data and changing an operating condition for a power conversion circuit based on the analysis information.

## Claims

### Claim 1

A timing controller comprising:
a load analysis circuit configured to analyze image data for each frame of a plurality of frames and to calculate a panel load for each frame of the plurality of frames; and
a communication circuit configured to generate a control signal corresponding to a size of the panel load and to transmit the control signal for changing a driving condition of a control circuit to a power management circuit including the control circuit,
wherein the driving condition of the control circuit includes an adjustment of a number of driven power switches driven in response to the control signal including information on the size of the panel load,
the adjustment of the number of driven power switches includes:
a first adjustment for driving a first power switch and for not driving a second power switch in case the size of the panel load is a first value,
a second adjustment for not driving the first power switch and for driving the second power switch in case the size of the panel load is a second value greater than the first value, and
a third adjustment for driving both the first power switch and the second power switch in case the size of the panel load is a third value greater than the second value.

### Claim 2 (depends on 1)

The timing controller of claim 1, wherein the load analysis circuit is configured to calculate the size of the panel load based on a size of a change of the image data between the plurality of frames.

### Claim 3 (depends on 1)

The timing controller of claim 1, wherein the load analysis circuit is configured to store the panel load for each frame of the plurality of frames in a memory.

### Claim 4 (depends on 1)

The timing controller of claim 1, wherein the communication circuit is configured to transmit the control signal to the power management circuit through a single wire.

### Claim 5 (depends on 1)

The timing controller of claim 1, wherein the communication circuit is configured to receive the image data and mode information from a host and generate the control signal by further using the mode information.

### Claim 6 (depends on 5)

The timing controller of claim 5, wherein the mode information includes information for indicating a power saving mode.

### Claim 7 (depends on 1)

The timing controller of claim 1, wherein the communication circuit is configured to transmit the control signal in a frame unit.