# US 12,602,923 B2 · Methods and apparatus to provide an efficient safety mechanism for signal processing hardware

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- Number: US 12,602,923 B2
- Document ID: US12602923B2
- Status: Granted
- Kind: B2
- Application number: 18/521,356
- Filed: 2023-11-28
- Published: 2024-03-28
- Granted: 2026-04-14
- Earliest claimed: 2017-12-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Mihir Narendra Mody; Niraj Nandan; Hetul Sanghvi; Manoj Koul
- Web page: https://patentgrep.com/patent/US12602923B2

## CPC

- G06V 10/98: Detection or correction of errors, e.g. by rescanning the pattern or by human intervention; Evaluation of the quality of the acquired patterns
- G06F 11/0736: {in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function (testing or monitoring of automated control systems G05B23/02)}
- G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)}
- G06V 10/36: Applying a local operator, i.e. means to operate on image points situated in the vicinity of a given point; Non-linear local filtering operations, e.g. median filtering
- G06T 7/0002: {Inspection of images, e.g. flaw detection}
- H04L 41/0677: Localisation of faults
- G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Systems and articles of manufacture provide an efficient safety mechanism for signal processing hardware. An example system includes a hardware accelerators, including a first hardware accelerator, and a second hardware accelerator coupled to the first hardware accelerator. Each of the first and second hardware accelerators includes a protected memory and an unprotected memory, and at least one of the hardware accelerators has an outlier filter. The system also includes a memory coupled to the hardware accelerators; and interface protectors, including a first interface protector coupled between the first hardware accelerator and the memory; a second interface protector coupled between the first hardware accelerator, the memory, and the second hardware accelerator; and a third interface protector coupled between the second hardware accelerator and the memory.

## Claims

### Claim 1

A system comprising:
a plurality of hardware accelerators, including a first hardware accelerator, and a second hardware accelerator coupled to the first hardware accelerator, each of the first hardware accelerator and the second hardware accelerator including a protected memory and an unprotected memory, and at least one of the plurality of hardware accelerators having an outlier filter;
a memory coupled to the plurality of hardware accelerators; and
a plurality of interface protectors, including:
a first interface protector coupled between the first hardware accelerator and the memory;
a second interface protector coupled between the first hardware accelerator, the memory, and the second hardware accelerator; and
a third interface protector coupled between the second hardware accelerator and the memory.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the plurality of hardware accelerators includes a third hardware accelerator coupled to the second hardware accelerator, the third hardware accelerator including a protected memory, an unprotected memory, and the outlier filter;
the plurality of interface protectors includes a fourth interface protector coupled between the third hardware accelerator and the memory; and
the third interface protector is coupled between the second hardware accelerator, the third hardware accelerator and the memory.

### Claim 3 (depends on 1)

The system of claim 1, wherein each of the first, second and third interface protectors includes a redundant bit determiner.

### Claim 4 (depends on 3)

The system of claim 3, wherein each of the first, second and third interface protectors is configured to receive a control signal and determine redundant bits using the corresponding redundant bit determiner.

### Claim 5 (depends on 1)

The system of claim 1, further comprising:
a multiplexer coupled to the first hardware accelerator; and
a de-multiplexer coupled to a last hardware accelerator of the plurality of hardware accelerators.

### Claim 6 (depends on 5)

The system of claim 5, wherein:
the multiplexer has an output and the de-multiplexer has an input;
the output of the multiplexer is coupled to an input of the first hardware accelerator via the first interface protector; and
the input of the de-multiplexer is coupled to an output of the last hardware accelerator via a last interface protector of the plurality of interface protectors.

### Claim 7 (depends on 1)

The system of claim 1, wherein the outlier filter includes:
a pixel array determiner; and
processing and adjusting circuitry coupled to the pixel array determiner.

### Claim 8 (depends on 1)

The system of claim 1, wherein:
the unprotected memory of the first hardware accelerator is configured to store a first set of data from an input signal, wherein the first set of data corresponds to a corruption of an output data set that is less than a threshold amount of corruption;
the protected memory of the first hardware accelerator is configured to store a second set of data from the input signal, wherein the second set of data corresponds to the corruption of the output data set that is more than the threshold amount of corruption; and
the first hardware accelerator further including logic configured to process the input signal.

### Claim 9 (depends on 8)

The system of claim 8, wherein the second hardware accelerator is coupled to receive an output signal including the first set of data, the second hardware accelerator including the outlier filter, the outlier filter configured to filter the first set of data to remove error.

### Claim 10 (depends on 9)

The system of claim 9, wherein the outlier filter is configured to:
determine a neighbor array of pixels for a select pixel of the first set of data;
determine a maximum value and a minimum value of the neighbor array of pixels; and
replace a value of the pixel with the minimum value when the value of the pixel is below the minimum value, and replace the value of the pixel with the maximum value when the value of the pixel is above the maximum value.

### Claim 11 (depends on 9)

The system of claim 9, wherein the outlier filter is configured to:
determine a neighbor array of pixels for a select pixel of the first set of data;
determine a distance between the select pixel and each of the pixels of the neighbor array of pixels;
determine an average distance based on the determined distances;
determine whether the average distance is greater than a threshold distance; and
when it is determined that the average distance is greater than the threshold distance, the outlier filter is further configured to:
determine an average value of values of the pixels of the neighbor array of pixels, and
replace a value of the select pixel with the average value.

### Claim 12

A non-transitory computer readable medium comprising instructions which, when executed by a device, cause the device to:
transmit, to a system of hardware accelerators, an input signal including redundant bits added to a control signal;
receive redundant bits from interface protectors of the system;
determine that the received redundant bits from a last in a signal chain of the interface protectors do not correspond to the added redundant bits;
compare respective subsets of the redundant bits received from respective ones of the interface protectors with the added redundant bits;
determine, based on the compare operation, where in the signal chain an error occurred; and
send an alert to a host device indicating signal chain location of the error.

### Claim 13 (depends on 12)

The non-transitory computer readable medium of claim 12, wherein the receive operation includes:
receive redundant bits directly from each of the interface protectors.

### Claim 14 (depends on 13)

The non-transitory computer readable medium of claim 13, wherein the determine operation includes:
determine, based on the compare operation, at which of the interface protectors the error occurred and which of the hardware accelerators caused the error.

### Claim 15 (depends on 14)

The non-transitory computer readable medium of claim 14, wherein the alert further indicates which of the hardware accelerators caused the error.

### Claim 16 (depends on 12)

The non-transitory computer readable medium of claim 12, wherein the input signal includes the control signal and a data signal, and the instructions further cause the device to:
determine the added redundant bits from the control signal.

### Claim 17 (depends on 16)

The non-transitory computer readable medium of claim 16, wherein the added redundant bits are determined using at least one of a parity check protocol, a cyclic redundancy check protocol, and a checksum protocol.

### Claim 18 (depends on 12)

The non-transitory computer readable medium of claim 12, wherein the instructions further cause the device to:
transmit the added redundant bits to the host device.

### Claim 19 (depends on 12)

The non-transitory computer readable medium of claim 12, wherein the input signal includes captured image data.