# US 12,602,607 B2 · Determining an implementation of a quantum program that has a minimized overall error rate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,607 B2 - Document ID: US12602607B2 - Status: Granted - Kind: B2 - Application number: 18/360,047 - Filed: 2023-07-27 - Published: 2025-11-27 - Granted: 2026-04-14 - Earliest claimed: 2023-07-27 - Assignees: Classiq Technologies Ltd. - Applicants: Classiq Technologies LTD. - Inventors: Amir Naveh; Shmuel Ur; Israel Reichental; Ravid Alon; Ofek Kirzner; Yehuda Naveh - Web page: https://patentgrep.com/patent/US12602607B2 ## CPC - G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation - G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)} - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers - G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control - G06N 10/60: Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms - G06N 10/80: Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method, apparatus and product comprising: obtaining alternative quantum circuits implementing a quantum program, each having a respective design error; identifying, for each quantum circuit, respective quantum resources that are used by the quantum circuit and are associated with respective hardware errors of a quantum computer; determining a total hardware error bound for the quantum circuit; determining a total error bound for the quantum circuit; applying a search algorithm over a plurality of total error bounds of the plurality of alternative quantum circuits, to identify an optimal total error bound that is associated with an optimal quantum circuit; and providing the optimal quantum circuit for execution on the quantum computer. ## Claims ### Claim 1 A method comprising: obtaining a plurality of alternative quantum circuits implementing a quantum program, each of the plurality of alternative quantum circuits having a respective design error; generating, by a compiler, a plurality of optimized quantum circuits, wherein the compiler receives the plurality of alternative quantum circuits, wherein the plurality of optimized quantum circuits implementing the plurality of alternative quantum circuits based on properties of a quantum computer; identifying, for each quantum circuit of the plurality of optimized quantum circuits, respective quantum resources that are used by the quantum circuit, the quantum resources comprising components that are associated with respective hardware errors of the quantum computer, the components comprising at least a quantum gate; based on the quantum resources and the respective hardware errors, determining a total hardware error bound for the quantum circuit; based on the total hardware error bound and based on a design error of the quantum circuit, determining a total error bound for the quantum circuit; applying a search algorithm over a plurality of total error bounds of the plurality of optimized quantum circuits, to identify an optimal total error bound that is lesser than other total error bounds, wherein the optimal total error bound is associated with an optimal quantum circuit from the plurality of optimized quantum circuits; and executing the optimal quantum circuit on the quantum computer. ### Claim 2 (depends on 1) The method of claim 1, wherein a hardware error of the quantum gate indicates an estimated probability of the quantum gate of the quantum computer not to function properly. ### Claim 3 (depends on 1) The method of claim 1, wherein the components comprise at least one of: a qubit, a cycle, and a defined type of gate. ### Claim 4 (depends on 1) The method of claim 1, wherein said obtaining comprises obtaining the plurality of alternative quantum circuits from a library that retains a plurality of quantum implementations of the quantum program. ### Claim 5 (depends on 1) The method of claim 1 further comprising obtaining the quantum program, wherein said obtaining the plurality of alternative quantum circuits comprises synthesizing the plurality of alternative quantum circuits based on the quantum program. ### Claim 6 (depends on 5) The method of claim 5, wherein said synthesizing comprises dynamically generating the plurality of alternative quantum circuits according to a respective plurality of design errors. ### Claim 7 (depends on 1) The method of claim 1, wherein the design error comprises an intended error for the quantum circuit that is intended to reduce a resource utilization of the quantum circuit. ### Claim 8 (depends on 1) The method of claim 1, wherein the search algorithm comprises at least one of: a gradual assent algorithm, a hill climbing algorithm, and a binary search algorithm. ### Claim 9 (depends on 1) The method of claim 1 further comprising: obtaining a plurality of quantum programs, the plurality of quantum programs comprising the quantum program; performing said generating for each of the plurality of quantum programs, thereby obtaining a second plurality of optimized quantum circuits; performing said identifying, said determining the total hardware error bound, and said determining the total error bound for each circuit of the second plurality of optimized quantum circuits; based on global constraints of the quantum computer, applying the search algorithm over total error bounds of the second plurality of optimized quantum circuits, the search algorithm is configured to find, for each of the plurality of quantum programs, an optimal quantum circuit from the second plurality of optimized quantum circuits that complies with the global constraints, and reduces an overall error rate of a joint quantum circuit that comprises a respective circuit from the second plurality of optimized quantum circuits for each of the plurality of quantum programs; and executing the joint quantum circuit on the quantum computer. ### Claim 10 (depends on 9) The method of claim 9, wherein the plurality of quantum programs comprises first and second quantum programs, wherein the second plurality of optimized quantum circuits comprises a first set of alternative quantum circuits that implement the first quantum program, and a second set of alternative quantum circuits that implement the second quantum program, each circuit of the first set of alternative quantum circuits having a different design error, each circuit of the second set of alternative quantum circuits having a different design error. ### Claim 11 An apparatus comprising a processor and coupled memory, said processor being adapted to: obtain a plurality of alternative quantum circuits implementing a quantum program, each of the plurality of alternative quantum circuits having a respective design error; generate, by a compiler, a plurality of optimized quantum circuits, wherein the compiler receives the plurality of alternative quantum circuits, wherein the plurality of optimized quantum circuits implementing the plurality of alternative quantum circuits based on properties of a quantum computer; identify, for each quantum circuit of the plurality of optimized quantum circuits, respective quantum resources that are used by the quantum circuit, the quantum resources comprising components that are associated with respective hardware errors of the quantum computer, the components comprising at least a quantum gate; based on the quantum resources and the respective hardware errors, determine a total hardware error bound for the quantum circuit, based on the total hardware error bound and based on a design error of the quantum circuit, determine a total error bound for the quantum circuit; apply a search algorithm over a plurality of total error bounds of the plurality of optimized quantum circuits, to identify an optimal total error bound that is lesser than other total error bounds, wherein the optimal total error bound is associated with an optimal quantum circuit from the plurality of optimized quantum circuits; and execute the optimal quantum circuit on the quantum computer. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the search algorithm comprises at least one of: a gradual assent algorithm, a hill climbing algorithm, and a binary search algorithm. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein a hardware error of the quantum gate indicates an estimated probability of the quantum gate of the quantum computer not to function properly. ### Claim 14 (depends on 11) The apparatus of claim 11, wherein the components comprise at least one of: a qubit, a cycle, and a defined type of gate. ### Claim 15 (depends on 11) The apparatus of claim 11, wherein said obtaining comprises obtaining the plurality of alternative quantum circuits from a library that retains a plurality of quantum implementations of the quantum program. ### Claim 16 (depends on 11) The apparatus of claim 11, wherein the processor is further adapted to obtain the quantum program, wherein said obtain the plurality of alternative quantum circuits comprises synthesizing the plurality of alternative quantum circuits based on the quantum program, wherein said synthesizing comprises dynamically generating the plurality of alternative quantum circuits according to a respective plurality of design errors. ### Claim 17 (depends on 11) The apparatus of claim 11, wherein the design error comprises an intended error for the quantum circuit that is intended to reduce a resource utilization of the quantum circuit. ### Claim 18 A system comprising: a quantum computer; a classical software agent configured to obtain a plurality of alternative quantum circuits implementing a quantum program, each of the plurality of alternative quantum circuits having a respective design error; a classical compiler configured to receive the plurality of alternative quantum circuits and to generate a plurality of optimized quantum circuits, wherein the plurality of optimized quantum circuits implementing the plurality of alternative quantum circuits based on properties of the quantum computer; wherein the classical software agent is configured to: identify, for each quantum circuit of the plurality of optimized quantum circuits, respective quantum resources that are used by the quantum circuit, the quantum resources comprising components that are associated with respective hardware errors of the quantum computer, the components comprising at least a quantum gate; based on the quantum resources and the respective hardware errors, determine a total hardware error bound for the quantum circuit; based on the total hardware error bound and based on a design error of the quantum circuit, determine a total error bound for the quantum circuit; and apply a search algorithm over a plurality of total error bounds of the plurality of optimized quantum circuits, to identify an optimal total error bound that is lesser than other total error bounds, wherein the optimal total error bound is associated with an optimal quantum circuit from the plurality of optimized quantum circuits; and wherein the quantum computer is configured to execute the optimal quantum circuit.