# US 12,602,575 B2 · Performing processing-in-memory operations related to pre-synaptic spike signals, and related methods and systems

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- Number: US 12,602,575 B2
- Document ID: US12602575B2
- Status: Granted
- Kind: B2
- Application number: 18/642,669
- Filed: 2024-04-22
- Published: 2024-08-15
- Granted: 2026-04-14
- Earliest claimed: 2019-09-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dmitri Yudanov; Sean S. Eilert; Hernan A. Castro; Ameen D. Akel
- Web page: https://patentgrep.com/patent/US12602575B2

## CPC

- G06N 3/063: using electronic means
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/088: Non-supervised learning, e.g. competitive learning
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06N 3/084: Backpropagation, e.g. using gradient descent
- G06N 5/046: Forward inferencing; Production systems
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

## Claims

### Claim 1

A system, comprising:
a memory array comprising a number of memory cells at intersections of a number of word lines and a number of bit lines; and
circuitry coupled to the memory array and configured to:
generate, in response to a first signal driven on a word line of the number of word lines, a second signal with a voltage, current, or timing characteristic, or combination thereof that either increases or decreases a conductance of a memory cell of the number of memory cells on a bit line of the number of bit lines; and
integrate current on the bit line intersecting the word line.

### Claim 2 (depends on 1)

The system of claim 1, wherein the circuitry is further configured to transmit a feedback signal to the bit line, wherein the feedback signal is a decaying bias.

### Claim 3 (depends on 1)

The system of claim 1, wherein the second signal is applied to each memory cell on the bit line.

### Claim 4 (depends on 1)

The system of claim 1, wherein the circuitry is further configured to generate a spike signal in response to a threshold potential value of a neuron driven on the bit line being met.

### Claim 5 (depends on 4)

The system of claim 4, wherein the conductance of the memory cell increases in response to the second signal if the first signal is driven on the word line before the spike signal is generated.

### Claim 6 (depends on 4)

The system of claim 4, wherein the conductance of the memory cell decreases in response to the second signal if the first signal is driven on the word line after the spike signal of is generated.

### Claim 7 (depends on 4)

The system of claim 4, wherein the circuitry is further configured to, in response to the first signal driven on the word line after generation of the spike signal, apply an individual decaying bias to each memory cell of the number of memory cells on the bit line.

### Claim 8 (depends on 4)

The system of claim 4, wherein the circuitry is further configured to, in response to the first signal driven on the word line before generation of the spike signal, apply another signal to one or more memory cells of the number of memory cells on the word line, wherein a conductance of the one or more memory cells returns to an original conductance state after a predetermined time duration.

### Claim 9 (depends on 4)

The system of claim 4, wherein the circuitry is further configured to, in response to the generation of the spike signal, apply a threshold modulating bias to another bit line of the number of bit lines intersecting the word line.

### Claim 10 (depends on 9)

The system of claim 9, wherein the threshold modulating bias is applied immediately after the generation of the spike signal.

### Claim 11 (depends on 1)

The system of claim 1, further comprising a memory controller configured to copy conductance on a second memory cell of the number of memory cells on a second bit line of the number of bit lines intersecting the word line to the memory cell.

### Claim 12

A method, comprising:
generating a first signal with a voltage, current, or timing characteristic, or combination thereof that modifies a conductance of a memory cell in a long-term potentiation (LTP) window of a spike timing dependent plasticity (STDP) characteristic;
transmitting the first signal to a bit line coupled to the memory cell; and
in response to generation of a spike signal of a neuron driven on the bit line, transmitting a feedback signal to each memory cell on the bit line, wherein the feedback signal is a decaying bias.

### Claim 13 (depends on 12)

The method of claim 12, further comprising driving a second signal on a word line coupled to the memory cell, wherein the first signal is generated responsive to the second signal.

### Claim 14 (depends on 12)

The method of claim 12, further comprising generating the spike signal of the neuron in response to a membrane potential of the neuron meeting a predetermined threshold.

### Claim 15 (depends on 12)

The method of claim 12, further comprising generating a decaying signal to change conductivity of the memory cell in a decaying manner.

### Claim 16 (depends on 12)

The method of claim 12, further comprising adjusting a conductance value of the memory cell according to the decaying bias, the conductance of the memory cell, or both.

### Claim 17

An electronic system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device; and
at least one memory device operably coupled to the at least one processor device and comprising:
a number of memory cells; and
circuitry configured to:
generate, in response to a first signal driven on a word line of the number of word lines, a second a signal with a voltage, current, or timing characteristic, or combination thereof that modifies a conductance of a memory cell of the number of memory cells;
transmit the second signal to a bit line coupled to the memory cell; and
transmit, in response to a spike signal of a neuron driven on the bit line, a decaying bias feedback signal to each memory cell on the bit line.

### Claim 18 (depends on 17)

The electronic system of claim 17, wherein the circuitry is further configured to generate the spike signal in response to a membrane potential of the neuron meeting a predetermined threshold.

### Claim 19 (depends on 18)

The electronic system of claim 18, wherein:
the conductance of the memory cell increases in response to the second signal if the first signal is driven on the word line before the spike signal is generated; and
the conductance of the memory cell decreases in response to the second signal if the first signal is driven on the word line after the spike signal of is generated.

### Claim 20 (depends on 17)

The electronic system of claim 17, wherein the circuitry is further configured to integrate current on the bit line.