# US 12,602,531 B1 · Multi-chip module (MCM) with multi-port unified memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,602,531 B1
- Document ID: US12602531B1
- Status: Granted
- Kind: B1
- Application number: 19/241,314
- Filed: 2025-06-17
- Granted: 2026-04-14
- Earliest claimed: 2021-11-25
- Assignees: Eliyan Corporation
- Applicants: Eliyan Corporation
- Inventors: Ramin Farjadrad
- Web page: https://patentgrep.com/patent/US12602531B1

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 2115/12: Printed circuit boards [PCB] or multi-chip modules [MCM]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

## Claims

### Claim 1

An integrated circuit (IC) base die to couple to a stack of memory die, the IC base die comprising:
a first port comprising a die-to-die (D2D) interface to couple to an IC device, the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
a second port comprising a memory interface to access a memory other than the stack of memory die; and
memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.

### Claim 2 (depends on 1)

The IC base die of claim 1, wherein:
the stack of memory die comprises a stack of High-Bandwidth Memory (HBM) die.

### Claim 3 (depends on 1)

The IC base die of claim 1, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 4 (depends on 1)

The IC base die of claim 1, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory; and
wherein the memory control circuitry comprises one of a graphics double data rate (GDDR) memory controller or a low-power double data rate LPDDR memory controller that corresponds to the graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 5 (depends on 1)

The IC base die of claim 1, further comprising:
mechanical interface circuitry to couple to a package substrate of a system-in-package (SiP); and
wherein the memory other than the stack of memory die is disposed external to the SiP.

### Claim 6 (depends on 1)

The IC base die of claim 1, wherein the first port comprises:
a first set of channel circuits to access the stack of memory die; and
a second set of channel circuits to access the memory other than the stack of memory die.

### Claim 7

A memory chiplet to couple to a package substrate of a system-in-package (SiP), the memory chiplet comprising:
a stack of memory die; and
an integrated circuit (IC) base die coupled to the stack of memory die, the IC base die comprising
a first port comprising a die-to-die (D2D) interface to couple to an IC device, the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
a second port comprising a memory interface to access a memory other than the stack of memory die; and
memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.

### Claim 8 (depends on 7)

The memory chiplet of claim 7, wherein:
the stack of memory die comprises a stack of High-Bandwidth Memory (HBM) die.

### Claim 9 (depends on 7)

The memory chiplet of claim 7, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 10 (depends on 7)

The memory chiplet of claim 7, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory; and
wherein the memory control circuitry comprises one of a graphics double data rate (GDDR) memory controller or a low-power double data rate LPDDR memory controller that corresponds to the graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 11 (depends on 7)

The memory chiplet of claim 7, further comprising:
mechanical interface circuitry to couple to a package substrate of a system-in-package (SiP); and
wherein the memory control circuitry is configured to control a memory, other than the stack of memory die, that is disposed external to the SiP.

### Claim 12 (depends on 7)

The memory chiplet of claim 7, wherein the first port comprises:
a first set of channel circuits to access the stack of memory die; and
a second set of channel circuits to access the memory other than the stack of memory die.

### Claim 13

A system-in-package (SiP) to couple to a base substrate, the SiP comprising:
a package substrate that is separate from the base substrate;
an integrated circuit device coupled to the package substrate;
a memory chiplet coupled to the package substrate, the memory chiplet comprising
a stack of memory die; and
an integrated circuit (IC) base die coupled to the stack of memory die, the IC base die comprising
a first port comprising a die-to-die (D2D) interface to couple to an IC device the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;
a second port comprising a memory interface to access a memory other than the stack of memory die; and
memory control circuitry to control memory access operations directed to the memory other than the stack of memory die.

### Claim 14 (depends on 13)

The SiP of claim 13, wherein:
the stack of memory die comprises a stack of High-Bandwidth Memory (HBM) die.

### Claim 15 (depends on 13)

The SiP of claim 13, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 16 (depends on 13)

The SiP of claim 13, wherein:
the memory other than the stack of memory die comprises one of graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory; and
wherein the memory control circuitry comprises one of a graphics double data rate (GDDR) memory controller or a low-power double data rate LPDDR memory controller that corresponds to the graphics double data rate (GDDR) memory or low-power double data rate LPDDR memory.

### Claim 17 (depends on 13)

The SiP of claim 13, further comprising:
mechanical interface circuitry to couple to a package substrate of a system-in-package (SiP); and
wherein the memory other than the stack of memory die is disposed external to the SiP.