US 12,602,529 B2Granted

Systems and methods for reducing congestion on network-on-chip

AssigneeAltera Corporation

InventorsRahul Pal, Ashish Gupta, Navid Azizi, Jeffrey Schulz, Yin Chong Hew, Ngo Gia Thuyet, George Chong Hean Ooi, Vikrant Kapila, Kok Kee Looi

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Abstract

Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Claims11

Dependent claims

A field-programmable gate array, comprising:

a network-on-chip (NoC) communicatively coupled to one or more internal components and one or more external components, the NoC comprising:
a first bridge configurable to receive data from the internal components;
a second bridge configurable to transmit data to the one or more external components;
one or more switches communicatively configurable to facilitate data transfer between the first bridge and the second bridge;
a buffer configurable to store data transferred from the one or more internal components to the one or more external components;
and
dynamic data throttling circuitry configurable to adjust a rate of flow of the data transferred from the one or more internal components to the one or more external components based at least upon receiving a first control signal from the buffer, a second control signal from the buffer, or both.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/854,341Filed 30 Jun 2022
Published: US 2022/0405453 A122 Dec 2022
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 13/4027
Coupling between buses: using bus bridges
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 9/3005
Arrangements for executing specific machine instructions: to perform operations for flow control
G06F 9/544
Interprogram communication: buffers; Shared memory; Pipes