# US 12,602,345 B2 · Multi-protocol retimer enabling transparent and non-transparent bridging for memory fabrics including PCIe, CXL, or UALink > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,345 B2 - Document ID: US12602345B2 - Status: Granted - Kind: B2 - Application number: 19/371,994 - Filed: 2025-10-28 - Published: 2026-02-26 - Granted: 2026-04-14 - Earliest claimed: 2023-12-13 - Assignees: UnifabriX Ltd. - Applicants: UnifabriX Ltd. - Inventors: Ronen Aharon Hyatt; Gaya Opal Hyatt; Ethan Sharon Hyatt - Web page: https://patentgrep.com/patent/US12602345B2 ## CPC - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and/or PCIe domains, addressing interoperability challenges. ## Claims ### Claim 1 A semiconductor device, comprising: an integrated circuit (IC) package comprising high speed differential I/O balls positioned according to ball grid array layout defined by a PCIe Retimer Supplemental Features and Standard BGA Footprint Specification; wherein PCIe denotes Peripheral Component Interconnect Express, and BGA denotes ball grid array: wherein the IC package comprises: a first interface configured to communicate according to a first protocol; a second interface configured to communicate according to a second protocol; and a computer configured to extract physical addresses carried in messages received from the first interface, translate the physical addresses, generate messages that carry the translated physical addresses, and send the messages via the second interface. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the entire IC package is compatible with the ball grid array layout defined by PCIe 5.0, 6.0, or 7.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein at least one of Pin Name VD_1 to VD_6 or VD_9 to VD_15 are incompatible with the ball grid array layout defined by PCIe 5.0, 6.0, or 7.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first protocol comprises CXL.mem, the first interface is configured to expose a Compute Express Link (CXL) type 2 device or a CXL type 3 device, the second protocol comprises CXL.cache, and the second interface is configured to expose a CXL type 1 device or a CXL type 2 device. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the CXL.mem protocol utilizes messages comprising first physical addresses (PAs) from a first Host Physical Address (HPA) space utilized by a first host coupled to the first interface, and wherein the CXL.cache protocol utilizes messages comprising second PAs from a second HPA space utilized by a second host coupled to the second interface. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first protocol comprises CXL.cache, the first interface is configured to expose a Compute Express Link (CXL) type 1 device or a CXL type 2 device, the second protocol comprises CXL.cache, and the second interface is configured to expose a CXL type 1 device or a CXL type 2 device. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the first protocol utilizes messages comprising first physical addresses (PAs) from a first Host Physical Address (HPA) space utilized by a first host coupled to the first interface, and the second protocol utilizes messages comprising second PAs from a second HPA space utilized by a second host coupled to the second interface. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the first protocol comprises CXL.mem, the first interface is configured to expose a Compute Express Link (CXL) type 2 device or a CXL type 3 device, the second protocol comprises CXL.mem, and the second interface is configured to expose a CXL Root Port. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first protocol utilizes messages comprising first physical addresses (PAs) from a first physical address space utilized by a first host coupled to the first interface, and the second protocol utilizes messages comprising second PAs from a second physical address space exposed by the Computer over the second interface. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first protocol comprises PCIe or CXL.io, the first interface is configured to expose an Endpoint, the second protocol comprises PCIe or CXL.io, and the second interface is configured to expose an Endpoint. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first protocol utilizes Transaction layer Packets (TLPs) or Protocol Data Units (PDUs) comprising first physical addresses (PAs) from a first Host Physical Address (HPA) space utilized by a first host coupled to the first interface, and the second protocol utilizes TLPs or PDUs comprising second PAs from a second HPA space utilized by a second host coupled to the second interface. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the first protocol utilizes at least one Unordered IO (UIO) Transaction Layer Packet (TLP) Type and at least 50% of Memory Requests transmitted by the first interface utilize Flit Mode (FM) TLP formats, and/or wherein the second protocol utilizes at least one of the TLP Types UIOMRd, UIOMWr, UIORdCpl, UIOWrCpl, UIORdCplD. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the computer is further configured to translate the physical addresses to enable access to memory regions storing Large Language Model (LLM) parameters distributed across multiple memory domains, whereby the translated physical addresses enable the first interface to access LLM model weights and activation data residing in a physical address space associated with the second interface. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the IC package is further compatible with power and ground pin distribution defined by PCIe 7.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein the first and second interfaces are configured to support a x4 lane configuration, comprising high-speed differential pairs arranged to support two sets of four lanes for data transmission, and wherein the IC package is further compatible with package dimensions defined for the x4 retimer by PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 16 (depends on 1) The semiconductor device of claim 1, wherein the first and second interfaces are configured to support a x8 lane configuration, comprising high-speed differential pairs arranged to support two sets of eight lanes for data transmission, and wherein the IC package is further compatible with package dimensions defined for the x8 retimer by PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 17 (depends on 1) The semiconductor device of claim 1, wherein the IC package is configured to support a x16 lane configuration, comprising high-speed differential pairs arranged to support two sets of sixteen lanes for data transmission, and wherein the IC package is further compatible with package dimensions defined for the x16 retimer by PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification. ### Claim 18 (depends on 1) The semiconductor device of claim 1, wherein the first and second interfaces support operation at data rates of 32.0 GT/s using non-return-to-zero (NRZ) signaling as defined in PCIe 5.0 specification, and support operation at 64.0 GT/s using four-level pulse amplitude modulation (PAM4) signaling as defined in PCIe 6.0 specification, thereby providing compatibility with PCIe 5.0 systems and with PCIe 6.0 systems. ### Claim 19 (depends on 1) The semiconductor device of claim 1, wherein the first and second interfaces are compatible with PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification, supporting data rates up to 64.0 GT/s and four-level pulse amplitude modulation (PAM4) signaling in addition to non-return-to-zero (NRZ) signaling, such that the semiconductor device is operable to negotiate data rates and signaling methods for both PCIe 5.0 and PCIe 6.0 systems. ### Claim 20 (depends on 1) The semiconductor device of claim 1, wherein the first and second interfaces further comprises ground pins distributed according to PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification, enabling improved signal integrity at data rates exceeding 32.0 GT/s. ### Claim 21 (depends on 1) The semiconductor device of claim 1, wherein the IC package is further compatible with PCIe 4.0 Retimer Supplemental Features and Standard BGA Footprint Specification, supporting data rates up to 16.0 GT/s. ### Claim 22 (depends on 1) The semiconductor device of claim 1, wherein the first interface is coupled to a first host via one or more switches, and/or wherein the second interface is coupled to a second host via one or more switches. ### Claim 23 A method of operating a semiconductor device, comprising: transmitting, according to a first protocol, via a first interface of an integrated circuit (IC) package, wherein the IC package comprises high speed differential I/O balls positioned according to ball grid array layout defined by a PCIe Retimer Supplemental Features and Standard BGA Footprint Specification; wherein PCIe denotes Peripheral Component Interconnect Express, and BGA denotes ball grid array: transmitting, according to a second protocol, via a second interface of the IC package; extracting, by a computer located in the IC package, first physical addresses carried in first messages received from the first interface; translating, by the computer, the first physical addresses to second physical addresses; generating second messages that carry the second physical addresses; and sending the second messages via the second interface. ### Claim 24 (depends on 23) The method of claim 23, wherein operating the first interface comprises operating according to CXL.mem semantics utilizing the first messages comprising the first physical addresses within a Host Physical Address (HPA) space utilized by a first host communicating with the first interface; and wherein operating the second interface comprises operating according to CXL.cache semantics utilizing the second messages comprising the second physical addresses within an HPA space utilized by a second host communicating with the second interface. ### Claim 25 (depends on 23) The method of claim 23, wherein operating the first interface comprises operating according to CXL.cache semantics utilizing the first messages comprising the first physical addresses within a Host Physical Address (HPA) space utilized by a first host communicating with the first interface; and wherein operating the second interface comprises operating according to CXL.cache semantics utilizing the second messages comprising the second physical addresses within an HPA space utilized by a second host communicating with the second interface. ### Claim 26 (depends on 23) The method of claim 23, wherein operating the first interface comprises operating according to CXL.mem semantics utilizing the first messages comprising the first physical addresses within a Host Physical Address (HPA) space utilized by a first host communicating with the first interface; and wherein operating the second interface comprises operating according to CXL.mem semantics utilizing the second messages comprising the second physical addresses within a physical address space exposed by the computer over the second interface. ### Claim 27 (depends on 23) The method of claim 23, wherein operating the first interface comprises operating according to PCIe or CXL.io semantics utilizing the first messages comprising the first physical addresses within a Host Physical Address (HPA) space utilized by a first host communicating with the first interface; and wherein operating the second interface comprises operating according to PCIe or CXL.io semantics utilizing the second messages comprising the second physical addresses within an HPA space utilized by a second host communicating with the second interface. ### Claim 28 (depends on 23) The method of claim 23, wherein operating the first and second interfaces comprises operating at data rates of 32.0 GT/s using non-return-to-zero (NRZ) signaling as defined in PCIe 5.0 specification, or operating at 64.0 GT/s using four-level pulse amplitude modulation (PAM4) signaling as defined in PCIe 6.0 specification, thereby providing compatibility with PCIe 5.0 systems and with PCIe 6.0 systems. ### Claim 29 (depends on 23) The method of claim 23, wherein operating the first and second interfaces comprises operating according to PCIe 6.0 Retimer Supplemental Features and Standard BGA Footprint Specification, supporting data rates up to 64.0 GT/s and four-level pulse amplitude modulation (PAM4) signaling in addition to non-return-to-zero (NRZ) signaling, such that the semiconductor device negotiates data rates and signaling methods for both PCIe 5.0 and PCIe 6.0 systems. ### Claim 30 (depends on 23) A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform the method of claim 23.