Software interrupt management system for symmetric multiprocessing devices
AssigneeSilicon Laboratories Inc.
InventorsLouis-Philippe Majeau, Jean Francois Deschenes
Life of this patent
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Abstract
A system and method of handling interrupts in a symmetric multiprocessing system is disclosed. The symmetric multiprocessing system may comprise a plurality of ARM processors, such as Cortex-M processors. All of the possible interrupt sources are routed to all of the processing units. A message handling unit (MHU) is used to communicate between processing units to relay information about the interrupts. A MHU interrupt service routine is used to handle the enabling and disabling of the various interrupt sources, as requested by the other processing unit. The MHU interrupt service routine also tracks whether the interrupt that is to be disabled is currently executing.
Claims18
A symmetric multiprocessor system, comprising:
- a first processing unit having a first interrupt controller and a first message handling unit (MHU);
- a second processing unit having a second interrupt controller and a second MHU;
- and
- one or more interrupt sources in communication with the first processing unit and the second processing unit;
- wherein a write by the first processing unit to the second MHU triggers an MHU interrupt in the second processing unit;
- and
- wherein the second processing unit comprises an MHU interrupt service routine (ISR) that is configured to:
- read a message from the second MHU after an MHU interrupt is triggered, wherein the message comprises a request from the first processing unit to configure the second interrupt controller;
- configure the second interrupt controller accordingly;
- and
- if the message is not requesting that an interrupt be disabled, transmit an acknowledgment to the first MHU.
A processing unit for use in a symmetric multiprocessor system, comprising:
- an interrupt controller;
- a message handling unit (MHU);
- and
- a memory comprising:
- a MHU interrupt service routine (ISR);
- and
- at least one additional ISR, having an exit hook;
- wherein the MHU ISR is executed when a message is written to the MHU;
- and
- the MHU ISR includes instructions to:
- read the message, wherein the message comprises a request to configure the interrupt controller;
- configure the interrupt controller accordingly;
- and
- transmit an acknowledgment if the request was not to disable an interrupt.
Dependencies are inferred from the claim text.