# US 12,602,286 B2 · Storage class memory, data processing method, and processor system

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,602,286 B2
- Document ID: US12602286B2
- Status: Granted
- Kind: B2
- Application number: 18/740,001
- Filed: 2024-06-11
- Published: 2024-10-03
- Granted: 2026-04-14
- Earliest claimed: 2021-12-13
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Xiaoming Zhu
- Web page: https://patentgrep.com/patent/US12602286B2

## CPC

- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1072: {in multilevel memories}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A plurality of memory chips included in the storage class memory are divided into at least one group. Each group includes a first-type memory chip and a second-type memory chip. The second-type memory chip is configured to store running error correction code, and the first-type memory chip is configured to store data and retry error correction code. The running error correction code is for performing first-level memory error correction on the data stored in the first-type memory chip in the same group. The retry error correction code is for performing, when the first-level memory error correction fails, second-level memory error correction on the data stored in the first-type memory chip.

## Claims

### Claim 1

A storage class memory, comprising:
a plurality of memory chips, wherein the plurality of memory chips include at least one group, wherein each group of the at least one group comprises a first-type memory chip and a second-type memory chip;
wherein the first-type memory chip is configured to store:
data; and
retry error correction code:
wherein the second-type memory chip is configured to store running error correction code for performing first-level memory error correction on the data stored in the first-type memory chip in the same group as the second-type memory chip; and
wherein the retry error correction code is for performing second-level memory error correction on the data stored in the first-type memory chip in case of failure of the first-level memory error correction.

### Claim 2 (depends on 1)

The storage class memory according to claim 1, wherein the first-type memory chip comprises M first-type banks and N second-type banks, wherein the M first-type banks are configured to store data, and wherein the N second-type banks are configured to store the retry error correction code.

### Claim 3 (depends on 2)

The storage class memory according to claim 2, wherein a unit data access amount of a respective first-type bank and a unit data access amount of a respective second-type bank each are a unit data access amount of one bit in a bit width of the first-type memory chip.

### Claim 4 (depends on 2)

The storage class memory according to claim 2, wherein the first-type memory chip further comprises a third-type bank, wherein the third-type bank is configured to implement a function of bad block management on a bank of the first-type memory chip.

### Claim 5 (depends on 1)

The storage class memory according to claim 1, wherein a bit width of the storage class memory meets a memory bit width indicated by a double data rate (DDR) protocol.

### Claim 6 (depends on 5)

The storage class memory according to claim 5, wherein a quantity of first-type memory chips and a quantity of second-type memory chips in each group are determined based on a bit width of the first-type memory chip, a bit width of the second-type memory chip, and the memory bit width indicated by the DDR protocol.

### Claim 7 (depends on 6)

The storage class memory according to claim 6, wherein the memory bit width indicated by the DDR protocol is 80 bits;
wherein both the bit width of the first-type memory chip and the bit width of the second-type memory chip are 8 bits;
wherein the storage class memory comprises ten memory chips divided into two groups, wherein each group of the two groups comprises four first-type memory chips and one second-type memory chip;
wherein a sum of bit widths of the four first-type memory chips and the second-type memory chip comprised in each group is 40 bits, and a unit data access amount of each bit is 16 bytes or 32 bytes.

### Claim 8

A data processing method, comprising:
performing, by a controller connected to at least one storage class memory and a processor, first-level memory error correction on data stored in a first-type memory chip of the at least one storage class memory; and
based on failure of the first-level memory error correction, obtaining, by the controller, the data stored in the first-type memory chip, and performing second-level memory error correction on the data stored in the first-type memory chip based on retry error correction code stored in the first-type memory chip, wherein the retry error correction code is for performing the second-level memory error correction on the data stored in the first-type memory chip in case of failure of the first-level memory error correction.

### Claim 9 (depends on 8)

The method according to claim 8, wherein performing the first-level memory error correction on the data stored in the first-type memory chip includes using hamming code; and
wherein performing the second-level memory error correction on the data stored in the first-type memory chip includes using low-density parity-check code.

### Claim 10 (depends on 8)

The method according to claim 8, wherein performing first-level memory error correction on the data stored in the first-type memory chip comprises: performing, by the controller, first-level memory error correction on a single bit in 128 bytes to 512 bytes of the data stored in the first-type memory chip; and
wherein performing second-level memory error correction on the data stored in the first-type memory chip comprises: performing, by the controller, second-level memory error correction on hundreds of bits in 2048 bytes to 4096 bytes of the data stored in the first-type memory chip.

### Claim 11 (depends on 8)

The method according to claim 8, further comprising:
converting, by the controller, instructions of the processor into instructions of the storage class memory, and converting instructions of the storage class memory into instructions of the processor.

### Claim 12

A processor system, comprising:
a storage class memory, comprising a plurality of memory chips, wherein the plurality of memory chips include at least one group, wherein each group of the at least one group comprises a first-type memory chip configured to store data and retry error correction code, wherein the retry error correction code is for performing second-level memory error correction on the data stored in the first-type memory chip in case of failure of the first-level memory error correction;
a processor; and
a controller separately connected to the processor and the storage class memory, wherein the controller is configured to:
perform first-level memory error correction on data stored in a respective first-type memory chip; and
obtain the data stored in the respective first-type memory chip and perform second-level memory error correction on the data stored in the respective first-type memory chip in case of failure of the first-level memory error correction performed on the data stored in the respective first-type memory chip.

### Claim 13 (depends on 12)

The system according to claim 12, wherein each group of the at least one group further comprises a second-type memory chip configured to store running error correction code for performing first-level memory error correction on data stored in a first-type memory chip in a same group as the second-type memory chip.

### Claim 14 (depends on 13)

The system according to claim 13, wherein a bit width of the storage class memory meets a memory bit width indicated by a double data rate (DDR) protocol.

### Claim 15 (depends on 14)

The system according to claim 14, wherein a quantity of first-type memory chips and a quantity of second-type memory chips in each group are determined based on a bit width of the first-type memory chip, a bit width of the second-type memory chip, and the memory bit width indicated by the DDR protocol.

### Claim 16 (depends on 15)

The system according to claim 15, wherein the memory bit width indicated by the DDR protocol is 80 bits;
wherein both the bit width of the first-type memory chip and the bit width of the second-type memory chip are 8 bits;
wherein the storage class memory comprises ten memory chips divided into two groups, wherein each group comprises four first-type memory chips and one second-type memory chip;
wherein a sum of bit widths of the four first-type memory chips and the second-type memory chip comprised in each group is 40 bits, and a unit data access amount of each bit is 16 bytes or 32 bytes.

### Claim 17 (depends on 15)

The system according to claim 15, wherein performing first-level memory error correction on the data stored in the respective first-type memory chip includes using hamming code; and
wherein performing second-level memory error correction on the data stored in the respective first-type memory chip includes using low-density parity-check code.

### Claim 18 (depends on 12)

The system according to claim 12, wherein the respective first-type memory chip comprises M first-type banks and N second-type banks, wherein the M first-type banks are configured to store data, and the N second-type bank are configured to store the retry error correction code.

### Claim 19 (depends on 18)

The system according to claim 18, wherein the respective first-type memory chip further comprises a third-type bank, wherein the third-type bank is configured to implement a function of bad block management on a bank of the first-type memory chip.

### Claim 20 (depends on 12)

The system according to claim 12, wherein performing first-level memory error correction on the data stored in the respective first-type memory chip comprises: performing first-level memory error correction on a single bit in 128 bytes to 512 bytes of the data stored in the respective first-type memory chip; and
wherein performing second-level memory error correction on the data stored in the respective first-type memory chip comprises: performing second-level memory error correction on hundreds of bits in 2048 bytes to 4096 bytes of the data stored in the respective first-type memory chip.