# US 12,602,282 B2 · Memory defect management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,282 B2 - Document ID: US12602282B2 - Status: Granted - Kind: B2 - Application number: 18/668,854 - Filed: 2024-05-20 - Published: 2025-11-20 - Granted: 2026-04-14 - Earliest claimed: 2024-05-20 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Ravi Kumar Siadri - Web page: https://patentgrep.com/patent/US12602282B2 ## CPC - G06F 11/1016: {Error in accessing a memory location, i.e. addressing error} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods are provided for implementing improved memory defect management. Bad pages, referring to portions of memory affected by memory errors, are identified by an operating system (“OS”) of a computing system. A list of bad pages may be periodically uploaded to a cloud data storage. The OS may also send the list of bad pages to a basic input/output system (“BIOS”) for repair of some of the bad pages. A list of repaired bad pages or corresponding status information may be sent to the OS. In some examples, the list of bad pages is compared with the list of repaired bad pages and may be updated accordingly. The list of bad pages may be compared with a previously uploaded list of bad pages that has been received from the cloud data storage. One list may be updated with, or replaced by, the other list based on the comparison. ## Claims ### Claim 1 A server, comprising: a basic input/output system (“BIOS”); a memory; and an operating system (“OS”) that executes computer executable instructions that cause the OS to perform operations comprising: sending, to the BIOS and retrieved from the memory, a first local list of defective memory addresses corresponding to a plurality of defective portions of the memory; receiving, from the BIOS, a list of repaired memory addresses corresponding to portions of the plurality of defective portions of the memory that have been repaired by the BIOS; comparing the list of repaired memory addresses with the first local list of defective memory addresses retrieved from the memory; based on a determination that the first local list of defective memory addresses lists repaired memory addresses contained in the list of repaired memory addresses, generating a second local list of defective memory addresses by updating the first local list of defective memory addresses based on the comparison; receiving, from a data storage over a network, a first uploaded list of defective memory addresses that was previously uploaded to the data storage by the OS; comparing the second local list of defective memory addresses with the first uploaded list of defective memory addresses; and based on a determination that the second local list of defective memory addresses is different from the first uploaded list of defective memory addresses, generating a second uploaded list of defective memory addresses by updating the first uploaded list of defective memory addresses based on the comparison, and uploading, to the data storage over the network, the second uploaded list of defective memory addresses. ### Claim 2 (depends on 1) The server of claim 1, wherein sending the first local list of defective memory addresses to the BIOS and receiving the first uploaded list of defective memory addresses are performed after a system reboot of the server. ### Claim 3 (depends on 1) The server of claim 1, wherein the plurality of defective portions includes at least one of a portion of the memory that has memory errors, a portion of the memory that has single bit errors, or a portion of the memory that has multi-bit errors. ### Claim 4 (depends on 1) The server of claim 1, wherein the memory includes at least one of an active memory, a main memory, or a random access memory (“RAM”). ### Claim 5 (depends on 1) The server of claim 1, wherein the operations further comprise: uploading, to the data storage over the network, updated lists of defective memory addresses on a periodic basis. ### Claim 6 (depends on 1) The server of claim 1, wherein receiving the first uploaded list of defective memory addresses or a subsequent uploaded list of defective memory addresses is one of performed upon reboot of the server, performed upon request by the OS, or performed on a periodic basis. ### Claim 7 A computer-implemented method, comprising: identifying, by an operating system (“OS”) of a server and from memory addresses that are absent from a first local list of defective memory addresses corresponding to a plurality of defective portions of a memory of the server, a first memory address corresponding to another defective portion of the memory, the first local list of defective memory addresses being stored in the memory; updating, by the OS, the first local list of defective memory addresses, by adding the identified first memory address to the first local list of defective memory addresses; uploading, by the OS and to a data storage over a network, the updated first local list of defective memory addresses; and after a system reboot of the server, receiving, by the OS and from the data storage over the network, a latest updated list of defective memory addresses; determining, by the OS, whether the latest updated list of defective memory addresses is consistent with the updated local list of defective memory addresses that is stored in the memory; and based on a determination that the latest updated list of defective memory addresses is inconsistent with the updated local list of defective memory addresses that is stored in the memory, performing one of: replacing the latest updated list of defective memory addresses, by uploading, by the OS and to the data storage over the network, the updated local list of defective memory addresses as retrieved from the memory; or replacing the updated local list of defective memory addresses that is stored in the memory with the latest updated list of defective memory addresses as received from the data storage over the network. ### Claim 8 (depends on 7) The computer-implemented method of claim 7, wherein the memory includes at least one of an active memory, a main memory, or a random access memory (“RAM”). ### Claim 9 (depends on 7) The computer-implemented method of claim 7, wherein identifying the first memory address is performed using a cyclic redundancy check. ### Claim 10 (depends on 7) The computer-implemented method of claim 7, further comprising: uploading, by the OS and to the data storage over the network, a latest updated local list of defective memory addresses on a periodic basis. ### Claim 11 (depends on 7) The computer-implemented method of claim 7, wherein replacing the latest updated list of defective memory addresses is performed based on a determination that the updated local list of defective memory addresses that is stored in the memory has been updated with a list of repaired memory addresses corresponding to portions of the plurality of defective portions of the memory that have been repaired by a basic input/output system (“BIOS”). ### Claim 12 (depends on 11) The computer-implemented method of claim 11, wherein replacing the updated local list of defective memory addresses is performed based on a determination that the updated local list of defective memory addresses that is stored in the memory remains unchanged after receiving memory repair status information from the BIOS. ### Claim 13 (depends on 12) The computer-implemented method of claim 12, further comprising: sending, by the OS and to the BIOS, a second local list of defective memory addresses, the second local list of defective memory addresses being retrieved from the memory and corresponding to a current updated local list of defective memory addresses; receiving, by the OS and from the BIOS, a current list of repaired memory addresses; comparing, by the OS, the current list of repaired memory addresses with the second local list of defective memory addresses retrieved from the memory; based on a determination that the second local list of defective memory addresses lists repaired memory addresses contained in the current list of repaired memory addresses, generating, by the OS, a third local list of defective memory addresses by updating the second local list of defective memory addresses based on the comparison; receiving, by the OS and from the data storage over the network, a first uploaded list of defective memory addresses that was uploaded to the data storage by the OS; comparing, by the OS, the third local list of defective memory addresses with the first uploaded list of defective memory addresses; and based on a determination that the third local list of defective memory addresses is different from the first uploaded list of defective memory addresses, generating, by the OS, a second uploaded list of defective memory addresses by updating the first uploaded list of defective memory addresses based on the comparison, and uploading, by the OS and to the data storage over the network, the second uploaded list of defective memory addresses. ### Claim 14 (depends on 13) The computer-implemented method of claim 13, further comprising: based on a determination that the second local list of defective memory addresses does not list repaired memory addresses contained in the current list of repaired memory addresses, comparing, by the OS, one of the current list of repaired memory addresses and the second local list of defective memory addresses with the first uploaded list of defective memory addresses that is received from the data storage; and based on a determination that the one of the current list of repaired memory addresses and the second local list of defective memory addresses is different from the first uploaded list of defective memory addresses, generating, by the OS, a fourth local list of defective memory addresses by replacing the second local list of defective memory addresses with the first uploaded list of defective memory addresses, and storing, by the OS, the fourth local list of defective memory addresses in the memory. ### Claim 15 A system, comprising: a processing system; and memory comprising computer executable instructions that, when executed, perform operations comprising: sending, to a basic input/output system (“BIOS”), a first local list of defective memory addresses corresponding to a plurality of defective portions of the memory; receiving, from the BIOS, a list of repaired memory addresses corresponding to portions of the plurality of defective portions of the memory that have been repaired by the BIOS; comparing the list of repaired memory addresses with the first local list of defective memory addresses retrieved from the memory; generating a second local list of defective memory addresses by updating the first local list of defective memory addresses based on the comparison; receiving a first uploaded list of defective memory addresses that was previously uploaded to data storage by an operating system (“OS”) of the system; comparing the second local list of defective memory addresses with the first uploaded list of defective memory addresses; and based on a determination that the second local list of defective memory addresses is different from the first uploaded list of defective memory addresses: generating a second uploaded list of defective memory addresses by updating the first uploaded list of defective memory addresses based on the comparison, and uploading, to the data storage, the second uploaded list of defective memory addresses. ### Claim 16 (depends on 15) The system of claim 15, wherein the sending the first local list of defective memory addresses to the BIOS is performed in response to a reboot of the system. ### Claim 17 (depends on 15) The system of claim 15, wherein the plurality of defective portions includes at least one of a portion of the memory that has memory errors, a portion of the memory that has single bit errors, or a portion of the memory that has multi-bit errors. ### Claim 18 (depends on 15) The system of claim 15, wherein the memory includes at least one of an active memory, a main memory, or a random access memory (“RAM”). ### Claim 19 (depends on 15) The system of claim 15, wherein the operations further comprise: uploading, to the data storage over the network, updated lists of defective memory addresses on a periodic basis. ### Claim 20 (depends on 15) The system of claim 15, wherein receiving the first uploaded list of defective memory addresses or a subsequent uploaded list of defective memory addresses is one of performed upon reboot of the system, performed upon request by the OS, or performed on a periodic basis.