# US 12,602,281 B2 · Memory system generating parity check codes using a randomizer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,281 B2 - Document ID: US12602281B2 - Status: Granted - Kind: B2 - Application number: 18/667,767 - Filed: 2024-05-17 - Published: 2025-06-19 - Granted: 2026-04-14 - Earliest claimed: 2023-12-19 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Zhe Zhang; Hua Tan; Xue Wu - Web page: https://patentgrep.com/patent/US12602281B2 ## CPC - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect. ## Claims ### Claim 1 A memory system, comprising: a memory device configured to store data and one or more parity check codes; a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule; and a codec coupled to the memory device and the randomizer, the codec configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data, the parity check codes to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect, wherein the codec is configured to generate the parity check codes by multiplying the pseudo-randomized numbers and the data and performing a bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data, the randomizer seed is selected based on the data and the pseudo-randomized numbers, or the randomizer includes a linear feedback shift register (LFSR), the LFSR is specified by a primitive polynomial, the LSFR includes a first number of cascaded shift registers, the data include a second number of pages, the one or more parity check codes include a third number of parity check codes, and two to a power of the first number is greater than multiplication of the second number minus one and the third number minus one. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the codec is configured to generate the parity check codes by multiplying the pseudo-randomized numbers and the data and performing the bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the codec is configured to generate a number of the parity check codes, and the randomizer is configured to generate the sequence of pseudo-randomized numbers using the randomizer seed in response to every the number of clocks of the clock signal according to the predetermined rule. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the randomizer seed is selected based on the data and the pseudo-randomized numbers. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the randomizer includes the linear feedback shift register (LFSR). ### Claim 6 (depends on 5) The memory system of claim 5, wherein the LFSR is specified by the primitive polynomial. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the LSFR includes the first number of cascaded shift registers, the data include the second number of pages, the one or more parity check codes include the third number of parity check codes, and two to the power of the first number is greater than multiplication of the second number minus one and the third number minus one. ### Claim 8 A method, comprising: generating, by using a randomizer, a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule; receiving data to be stored in a memory device; generating one or more parity check codes according to the pseudo-randomized numbers and the data and writing the parity check codes and the data to the memory device when a write operation is performed; and recovering at least one of the data stored in the memory device using the one or more parity check codes when a read operation is performed and the at least one of the data stored in the memory device is incorrect, wherein the parity check codes are generated by multiplying the pseudo-randomized numbers and the data and performing a bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data, the randomizer seed is selected based on the data and the pseudo-randomized numbers, or the randomizer includes a linear feedback shift register (LFSR), the LFSR is specified by a primitive polynomial, the LSFR includes a first number of cascaded shift registers, the data include a second number of pages, the one or more parity check codes include a third number of parity check codes, and two to a power of the first number is greater than multiplication of the second number minus one and the third number minus one. ### Claim 9 (depends on 8) The method of claim 8, wherein the parity check codes are generated by multiplying the pseudo-randomized numbers and the data and performing the bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data. ### Claim 10 (depends on 8) The method of claim 8, wherein a number of the parity check codes are generated, and the sequence of pseudo-randomized numbers are generated by using the randomizer seed in response to every the number of clocks of the clock signal according to the predetermined rule. ### Claim 11 (depends on 8) The method of claim 8, wherein the randomizer seed is selected based on the data and the pseudo-randomized numbers. ### Claim 12 (depends on 8) The method of claim 8, wherein the randomizer includes the linear feedback shift register (LFSR). ### Claim 13 (depends on 12) The method of claim 12, wherein the LFSR is specified by the primitive polynomial. ### Claim 14 (depends on 13) The method of claim 13, wherein the LSFR includes the first number of cascaded shift registers, the data include the second number of pages, the one or more parity check codes include the third number of parity check codes, and two to the power of the first number is greater than multiplication of the second number minus one and the third number minus one. ### Claim 15 A memory controller, comprising: a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule; and a codec coupled to the randomizer, the codec configured to generate one or more parity check codes according to the pseudo-randomized numbers and data to be stored in a memory device, the parity check codes to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect, wherein the codec is configured to generate the panty check codes by multiplying the pseudo-randomized numbers and the data and performing a bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data, the randomizer seed is selected based on the data and the pseudo-randomized numbers, or the randomizer includes a linear feedback shift register (LFSR), the LFSR is specified by a primitive polynomial and includes a first number of cascaded shift registers, the data include a second number of pages, the one or more parity check codes include a third number of parity check codes, and two to a power of the first number is greater than multiplication of the second number minus one and the third number minus one. ### Claim 16 (depends on 15) The memory controller of claim 15, wherein the codec is configured to generate the parity check codes by multiplying the pseudo-randomized numbers and the data and performing the bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data. ### Claim 17 (depends on 15) The memory controller of claim 15, wherein the codec is configured to generate a number of the panty check codes, and the randomizer is configured to generate the sequence of pseudo-randomized numbers using the randomizer seed in response to every the number of clocks of the clock signal according to the predetermined rule. ### Claim 18 (depends on 15) The memory controller of claim 15, wherein the randomizer seed is selected based on the data and the pseudo-randomized numbers. ### Claim 19 (depends on 15) The memory controller of claim 15, wherein the randomizer includes the linear feedback shift register (LFSR). ### Claim 20 (depends on 19) The memory controller of claim 19, wherein the LFSR is specified by the primitive polynomial and includes the first number of cascaded shift registers, the data include the second number of pages, the one or more parity check codes include the third number of parity check codes, and two to the power of the first number is greater than multiplication of the second number minus one and the third number minus one.