Systems and methods for debugging multi-core processors with configurable isolated partitions

A method, comprising:

• receiving, at a System Interface (SI) of a hardware accelerator having a plurality of multi-cluster tiles (MCTs), wherein each MCT is allocated to one of four quartiles and comprises a plurality of processor cores and a dedicated cross-trigger matrix (CTM) communicatively coupled to the respective plurality of processor cores, an indication of configuration of a plurality of isolated partitions of processor cores;
• determining, by the SI, that a first MCT of the plurality of MCTs is in a first quartile of the four quartiles and includes a first set of processor cores in a first isolated partition out of the plurality of isolated partitions;
• determining, by the SI, that a second MCT of the plurality of MCTs is in a second quartile of the four quartiles and includes a second set of processor cores in the first isolated partition out of the plurality of isolated partitions;
• and
• controlling a first CTM of the first MCT and a second CTM of the second MCT to disable a portion of a debug network associated with the first isolated partition by disabling, by the SI, one or more buses between two or more of the plurality of MCTs via the dedicated cross-trigger matrix to create a plurality of isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.

A hardware accelerator, comprising:

• an isolated partition control circuit coupled to a plurality of processor cores within multi-cluster tiles (MCTs), wherein each MCT is allocated to one set of a plurality of MCT sets, the isolated partition control circuit configured to dynamically partition the plurality of processor cores into a plurality of isolated partitions to prevent an application executed on one more processor cores of a first isolated partition from corrupting or interfering with another application executed on a different one or more processor cores of a second isolated partition;
• and
• a System Interface (SI) configured to:
• determine that a first MCT of the plurality of MCTs is in a first set of the plurality of sets and is associated with a first set of processor cores in a first isolated partition out of the plurality of isolated partitions,
• determine that a second MCT of the plurality of MCTs is in a second set of the plurality of sets and includes a second set of processor cores in the first isolated partition out of the plurality of isolated partitions, and
• control a first CTM of the first MCT and a second CTM of the second MCT to disable one or more buses between two or more of the plurality of MCTs to create a plurality of isolated debug networks wherein a portion of the plurality of isolated debug networks associated the first isolated portion is disabled, each isolated debug network corresponding to a distinct isolated partition.