System-level coordinated resilience
AssigneeMicron Technology, Inc.
InventorDavid Andrew Roberts
Life of this patent
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Abstract
A method performed by a distributed computing system is described. The distributed computing system includes one or more host nodes and a main memory connected to the one or more host nodes by a fabric interconnect. The method includes receiving, by an application program interface (API) of a host node, a function call from an application of a host device, the function call including a pointer to a memory object and a level of reliability for operations involving the memory object; and configuring system reliability features included in one or both of the fabric interconnect and memory devices of the main memory according to the level of reliability in the function call.
Claims17
A method performed by a distributed computing system that includes one or more host nodes and a main memory connected to the one or more host nodes by a fabric interconnect, the method comprising:
- receiving, by an application program interface (API) of a host node, a function call from an application of a host device, the function call including a pointer to a memory object and a level of reliability for operations involving the memory object;
- identifying memory device reliability features included in memory devices of the main memory from a lookup table stored in the main memory that indexes the IC die level error detection components, the memory-device level error detection components, and a system level error detection component according to levels of reliability for the memory object;
- and
- enabling identified memory device reliability features according to the level of reliability in the function call.
A non-transitory computer readable storage medium including instructions, that when performed by processing circuitry of a host node of a distributed computing system, cause the host node to perform operations including:
- configuring a reliability library that includes an application program interface (API);
- receiving, by the API, a function call from a client application of the host node, the function call including a pointer to a memory object and a level of reliability for operations involving the memory object;
- identifying memory device reliability features included in memory devices of a main memory of the distributed computing system by reading a lookup table stored in memory that indexes the IC die level error detection components, the memory-device level error detection components, and a system level error detection component according to levels of reliability for the memory object;
- and
- sending a command to enable the identified memory device reliability features according to the level of reliability in the function call.
A memory system of a distributed computing system, the memory system comprising:
- multiple memory devices, each memory device including:
- multiple integrated circuit (IC) memory dies;
- and
- a memory controller including:
- an IC die level error detection component to correct errors in a single IC die;
- and
- a memory-device level error detection component to correct errors when an IC die fails;
- a switch fabric coupled to the multiple memory devices;
- and
- a lookup table stored in memory that indexes the IC die level error detection components, the memory-device level error detection components, and a system level error detection component to levels of reliability for the memory object;
- wherein the memory controllers of the multiple memory devices are configured to receive commands to allocate a memory address range to a memory object and selectively enable one or more of the IC die level error detection component and the memory-device level error detection component for the memory address range.
Dependencies are inferred from the claim text.