# US 12,602,272 B2 · Circuitry for routing and delay correction in a multi-functional unit system

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- Number: US 12,602,272 B2
- Document ID: US12602272B2
- Status: Granted
- Kind: B2
- Application number: 18/094,182
- Filed: 2023-01-06
- Published: 2024-07-11
- Granted: 2026-04-14
- Earliest claimed: 2023-01-06
- Assignees: Mellanox Technologies, Ltd.
- Applicants: Mellanox Technologies, Ltd.
- Inventors: Diane Orf; Mark Rosenbluth; Michael Cotsford; Rui Xu; Shreya Tekade
- Web page: https://patentgrep.com/patent/US12602272B2

## CPC

- G06F 9/542: {Event management; Broadcasting; Multicasting; Notifications}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit includes a set of functional units having at least a first functional unit and a second functional unit. The first functional unit includes first processing circuitry and a first circuit coupled to the first processing circuitry to receive a message from the second functional unit of the set of functional units. The first circuit is further to delay the message for the first processing circuitry for a predetermined duration, where the predetermined duration is based at least in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.

## Claims

### Claim 1

An integrated circuit comprising:
a set of functional units comprising at least a first functional unit and a second functional unit, wherein the first functional unit comprises:
first processing circuitry; and
a first delay circuit located within the first functional unit and coupled to the first processing circuitry, wherein the first delay circuit comprises a plurality of delay components, and wherein the first delay circuit is to:
receive a message from the second functional unit of the set of functional units; and
delay the message for the first processing circuitry for a predetermined duration using a number of the plurality of delay components, wherein the predetermined duration is based at least in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the set of functional units comprises at least a third functional unit comprising:
second processing circuitry; and
a second delay circuit located within the third functional unit and coupled to the second processing circuitry, wherein the second delay circuit comprises a second plurality of delay components, and wherein the second delay circuit is to:
receive the message from the second functional unit of the set of functional units; and
delay the message for the second processing circuitry for a second predetermined duration using a number of the second plurality of delay components, wherein the second predetermined duration is based at least in part on a third value representing a third distance between the third functional unit and the second functional unit and the second value representing the second distance between the second functional unit and the functional unit of the set of functional units that is farthest away from the second functional unit.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the first processing circuitry is to process the message at a same time as the second processing circuitry.

### Claim 4 (depends on 2)

The integrated circuit of claim 2, wherein the predetermined duration is different from the second predetermined duration.

### Claim 5 (depends on 2)

The integrated circuit of claim 2, wherein:
the message is received at the first delay circuit at a first time; and
the message is received at the second delay circuit at a second time after the first time.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the first value indicates a third distance between the first functional unit and the second functional unit in a first direction and a fourth distance between the first functional unit and the second functional unit in a second direction.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein:
the message is a first type of message to be processed at two or more functional units at a same time; and
the second functional unit is to transmit messages of the first type via a second circuit and transmit messages of a second type via a mesh interconnect.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the message indicates an event or an initiation of a timer.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the predetermined duration is based on a difference between the second value and the first value.

### Claim 10

A device comprising:
a first functional unit of a set of functional units, the first functional unit comprising:
processing circuitry; and
a first delay circuit located within the first functional unit and coupled to the processing circuitry, wherein the first delay circuit comprises a plurality of delay components, and wherein the first delay circuit is to:
receive a message from a second functional unit of the set of functional units; and
delay the message for the processing circuitry for a predetermined duration using a number of the delay components, wherein the predetermined duration is based at least in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.

### Claim 11 (depends on 10)

The device of claim 10, wherein the processing circuitry is to process the message at a same time as a third functional unit of the set of functional units.

### Claim 12 (depends on 10)

The device of claim 10, wherein:
the message is a first type of message to be processed at two or more functional units at a same time; and
the second functional unit is to transmit messages of the first type via a second circuit and transmit messages of a second type via a mesh interconnect.

### Claim 13 (depends on 10)

The device of claim 10, wherein the first value indicates a third distance between the first functional unit and the second functional unit in a first direction and a fourth distance between the first functional unit and the second functional unit in a second direction.

### Claim 14 (depends on 10)

The device of claim 10, wherein the message indicates an event or an initiation of a timer.

### Claim 15 (depends on 10)

The device of claim 10, wherein the predetermined duration is based on a difference between the second value and the first value.

### Claim 16

A method of operating an integrated circuit with a set of functional units, the method comprising:
receiving, at a first delay circuit located within a first functional unit, a message from a second functional unit;
delaying, using a number of delay components of the first delay circuit, the message for a predetermined duration for first processing circuitry of the first functional unit, wherein the predetermined duration is based at least in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit; and
processing, using the first processing circuitry, the message after the predetermined duration.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
receiving, at a second delay circuit located within a third functional unit, the message from the second functional unit;
delaying, using a number of delay components of the second delay circuit, the message for a second predetermined duration for second processing circuitry of the third functional unit, wherein the second predetermined duration is based at least in part on a third value representing a third distance between the third functional unit and the second functional unit and the second value representing the second distance between the second functional unit and the functional unit of the set of functional units that is farthest away from the second functional unit; and
processing, using the second processing circuitry, the message after the second predetermined duration.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first processing circuitry is to process the message at a same time as the second processing circuitry.

### Claim 19 (depends on 17)

The method of claim 17, wherein the predetermined duration is different from the second predetermined duration.

### Claim 20 (depends on 17)

The method of claim 17, wherein:
the message is received at the first delay circuit at a first time; and
the message is received at the second delay circuit at a second time after the first time.