Processor, physical register management method, and electronic apparatus
AssigneeHygon Information Technology Co., Ltd.
InventorYaxuan Yu
Life of this patent
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Abstract
A processor, a physical register management method, and an electronic apparatus. The processor includes: a plurality of physical registers, which are configured to be multiplexed by a plurality of threads executed on the processor, and a thread information storage apparatus, which is configured to record a correlation between the plurality of physical registers and the plurality of threads. A correlation between a physical register and a thread is recorded by using a thread information storage apparatus, such that when a physical register number is broadcasted in error due to a fault occurring in hardware or for another reason, error correction can be realized in a timely manner, thereby preventing a subsequent series of errors and ensuring the normal operation of a processor.
Claims17
A processor, comprising:
- a plurality of physical registers, configured to be multiplexed by a plurality of threads executed on the processor;
- and
- a thread information storage apparatus, configured to record a corresponding relationship between the plurality of physical registers and the plurality of threads;
- wherein the processor further comprises a controller, and
- wherein the controller is configured to modify the corresponding relationship in the thread information storage apparatus in response to one of the plurality of physical registers being allocated to one of the plurality of threads and/or one of the plurality of physical registers being released.
A physical register management method, comprising:
- enabling a plurality of physical registers to be multiplexed by a plurality of threads executed on a processor;
- recording a corresponding relationship between the plurality of physical registers and the plurality of threads by using a thread information storage apparatus;
- and
- modifying the corresponding relationship in the thread information storage apparatus in response to one of the plurality of physical registers being allocated to one of the plurality of threads and/or one of the plurality of physical registers being released.
An electronic device, comprising a processor, wherein the processor comprises:
- a plurality of physical registers, configured to be multiplexed by a plurality of threads executed on the processor;
- and
- a thread information storage apparatus, configured to record a corresponding relationship between the plurality of physical registers and the plurality of threads;
- wherein the processor further comprises a controller, amd
- wherein the controller is configured to modify the corresponding relationship in the thread information storage apparatus in response to one of the plurality of physical registers being allocated to one of the plurality of threads and/or one of the plurality of physical registers being released.
Dependencies are inferred from the claim text.