Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage

A system, comprising:

• a memory to store data;
• a processor, communicatively coupled to the memory, to execute a neural network application;
• and
• an accelerator circuit comprising:
• an input circuit block comprising an input processor to perform a first task of the neural network application;
• a filter circuit block comprising a filter processor to perform a second task of the neural network application;
• a post-processing circuit block comprising a post-processing processor to perform a third task of the neural network application;
• an output circuit block comprising an output processor to perform a fourth task of the neural network application;
• and
• a plurality of general-purpose registers communicatively coupled to the input circuit block and the filter circuit block,
• wherein a producer stage is to supply data values to a consumer stage, and wherein operation of the consumer stage is on hold until a start flag stored in a first general-purpose register of the plurality of general-purpose registers is set by the producer stage, wherein the input circuit block, the filter circuit block, the post-processing circuit block, and the output circuit block form an execution pipeline,
• wherein the input circuit block further comprises a first instruction memory, a first data memory, and a first program counter (PC), wherein the first instruction memory is to store first instructions of the first task specified according to a first instruction set architecture (ISA) of the input processor, wherein the first PC is to store an address of a current first instruction to be executed by a first processor, and wherein the input processor is to execute the first instructions using first data stored in the first data memory to perform the first task,
• wherein the filter circuit block further comprises a second instruction memory, a second data memory, and a second PC, wherein the second instruction memory is to store second instructions of the second task specified according to a second ISA of the filter processor, wherein the second PC is to store an address of a current second instruction to be executed by a second processor, and wherein the filter processor is to execute the second instructions using second data stored in the second data memory to perform the second task,
• wherein the post-processing circuit block further comprises a third instruction memory, a third data memory, and a third PC, wherein the third instruction memory is to store third instructions of the third task specified according to a third ISA of the post-processing processor, wherein the third PC is to store an address of a current third instruction to be executed by a third processor, and wherein the post-processing processor is to execute the third instructions using third data stored in the third data memory to perform the third task;
• and
• wherein the output circuit block further comprises a fourth instruction memory, a fourth data memory, and a fourth PC, wherein the fourth instruction memory is to store fourth instructions of the fourth task specified according to a fourth ISA of the output processor, wherein the fourth PC is to store an address of a current fourth instruction to be executed by a fourth processor, and wherein the output processor is to execute the fourth instructions using fourth data stored in the fourth data memory to perform the fourth task.