# US 12,602,213 B2 · Scalable approximate counting > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,213 B2 - Document ID: US12602213B2 - Status: Granted - Kind: B2 - Application number: 18/199,486 - Filed: 2023-05-19 - Published: 2024-10-03 - Granted: 2026-04-14 - Earliest claimed: 2023-03-30 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Andrew Edward Ayers - Web page: https://patentgrep.com/patent/US12602213B2 ## CPC - G06F 8/443: {Optimisation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for implementing an intentionally approximate counting scheme are disclosed. A code counter is accessed. The counter updates a count that is approximately representative of a number of times the code is called. The counter operates in a first mode where the counter updates the count by a value of 1 and where a probability by which the counter updates the count is set to a value of 1. The counter switches from operating in the first mode to operating in a second mode. The counter now updates the count by a value of N, where N is an integer larger than 1. The probability by which the counter updates the count is set to a value of 1/N such that, despite multiple calls being made to the code, the count is updated in accordance with the 1/N probability. The counter continues to update the count. ## Claims ### Claim 1 A computer system that implements an intentionally approximate counting scheme, said computer system comprising: a processor system; and a storage system that stores instructions that are executable by the processor system to cause the computer system to: access a counter that is included in a portion of code, wherein the counter is structured to update a count that is approximately representative of a number of times the code portion is called or executed, and wherein the code portion is called or executed by a central processing unit (CPU); cause the counter to operate in a first mode, wherein the first mode is a mode in which the counter updates the count by a value of 1, and wherein, while the counter is operating in the first mode, a probability by which the counter updates the count is set to a value of 1 such that the counter updates the count each time the code portion is called or executed; determine the count has reached a first threshold while the counter is operating in the first mode; cause the counter to switch from operating in the first mode to operating in a second mode, wherein the second mode is a mode in which the counter updates the count by a value of N, where N is an integer larger than 1, and wherein, while the counter is operating in the second mode, the probability by which the counter updates the count is set to a value of 1/N such that, despite multiple calls being made to the code portion, the count is updated in accordance with the 1/N probability; cause the counter, which is now in the second mode, to continue to update the count, wherein the count is updated in accordance with the 1/N probability, and wherein the counter updates the count by the value of N; and write, each time the count is updated, a value of the count to the storage system. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the code portion is called or executed by a thread. ### Claim 3 (depends on 1) The computer system of claim 1, wherein the count is approximately representative of the number of times the code portion is called or executed when the count is within a determined tolerance level of the number of times the code portion is called or executed. ### Claim 4 (depends on 3) The computer system of claim 3, wherein the determined tolerance level is between about 1-2%. ### Claim 5 (depends on 1) The computer system of claim 1, wherein the counter is one of a plurality of counters that are included in the code. ### Claim 6 (depends on 5) The computer system of claim 5, wherein a number of counters included in the plurality of counters exceeds 50. ### Claim 7 (depends on 1) The computer system of claim 1, wherein the code is subsequently optimized. ### Claim 8 (depends on 1) The computer system of claim 1, wherein the counter is a contended resource in which multiple calling entities are attempting to use. ### Claim 9 (depends on 1) The method of claim 1, wherein the code portion is called or executed by a central processing unit. ### Claim 10 (depends on 1) The method of claim 1, wherein the counter, when operating in the first mode, is a deterministic counter. ### Claim 11 (depends on 1) The method of claim 1, wherein the counter, when operating in the second mode, is a probabilistic counter. ### Claim 12 (depends on 1) The method of claim 1, wherein the first threshold is set to a count value of over 8,000 counts. ### Claim 13 (depends on 1) The method of claim 1, wherein the first threshold is set to a count value that is over 8,000 counts and less than 10,000 counts. ### Claim 14 (depends on 1) The method of claim 1, wherein the first threshold is set to a count value that is over 5,000 counts. ### Claim 15 (depends on 1) The method of claim 1, wherein the first threshold is set to a count value that is less than 15,000 counts. ### Claim 16 A method for implementing an intentionally approximate counting scheme, said method comprising: accessing a counter that is included in a portion of code, wherein the counter is structured to update a count that is approximately representative of a number of times the code portion is called or executed; causing the counter to operate in a first mode, wherein the first mode is a mode in which the counter updates the count by a value of 1, and wherein, while the counter is operating in the first mode, a probability by which the counter updates the count is set to a value of 1 such that the counter updates the count each time the code portion is called or executed; determining the count has reached a first threshold while the counter is operating in the first mode; causing the counter to switch from operating in the first mode to operating in a second mode, wherein the second mode is a mode in which the counter updates the count by a value of N, where N is an integer larger than 1, and wherein, while the counter is operating in the second mode, the probability by which the counter updates the count is set to a value of 1/N such that, despite multiple calls being made to the code portion, the count is updated in accordance with the 1/N probability; causing the counter, which is now in the second mode, to continue to update the count, wherein the count is updated in accordance with the 1/N probability, and wherein the counter updates the count by the value of N; and writing, each time the count is updated, a value of the count to a storage system. ### Claim 17 (depends on 16) The method of claim 16, wherein the counter is one of a plurality of counters that are included in the code, and wherein a number of counters included in the plurality of counters exceeds 100. ### Claim 18 A computer system comprising: a processor system; and a storage system that stores instructions that are executable by the processor system to cause the computer system to: access a counter that is included in a portion of code, wherein the counter is structured to update a count that is approximately representative of a number of times the code portion is called or executed; cause the counter to operate in a first mode, wherein the first mode is a mode in which the counter updates the count by a value of 1, and wherein, while the counter is operating in the first mode, a probability by which the counter updates the count is set to a value of 1 such that the counter updates the count each time the code portion is called or executed; determine the count has reached a first threshold while the counter is operating in the first mode; cause the counter to switch from operating in the first mode to operating in a second mode, wherein the second mode is a mode in which the counter updates the count by a value of N, where N is an integer larger than 1, and wherein, while the counter is operating in the second mode, the probability by which the counter updates the count is set to a value of 1/N such that, despite multiple calls being made to the code portion, the count is updated in accordance with the 1/N probability; cause the counter, which is now in the second mode, to continue to update the count, wherein the count is updated in accordance with the 1/N probability, and wherein the counter updates the count by the value of N; and write, each time the count is updated, a value of the count to the storage system. ### Claim 19 (depends on 18) The computer system of claim 18, wherein the counter is a contended resource. ### Claim 20 (depends on 18) The computer system of claim 18, wherein the counter, when operating in the first mode, is a deterministic counter.