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US 12,602,200 B2Granted
Analog multiply-accumulate unit for multibit in-memory cell computing
AssigneeIntel Corporation
InventorsHechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte
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Abstract
Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.
Claims25
A computing system comprising:
- a processor;
- a memory array to store and output digital signals corresponding to bits of a multibit value;
- and
- a multiply-accumulator (MAC), wherein the MAC includes a plurality of multipliers, and the plurality of multipliers include a plurality of capacitors including a group of capacitors and a further group of capacitors, a plurality of switches, and a plurality of branches that include the plurality of switches and the group of capacitors;
- wherein the plurality of multipliers are configured to:
- receive, by the plurality of switches, the digital signals from the memory array,
- execute multibit computation operations with the plurality of capacitors and the plurality of switches forming a C-2C ladder based on the digital signals by controlling the plurality of switches using the digital signals to electrically connect or disconnect an input analog signal to the group of capacitors, and
- generate an output analog signal based on the multibit computation operations.
5 more elements
A semiconductor apparatus comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic comprising:
- a memory array to store and output digital signals corresponding to bits of a multibit value;
- and
- a multiply-accumulator (MAC) connected to the memory array, wherein the MAC includes a plurality of multipliers, and the plurality of multipliers include a plurality of capacitors including a group of capacitors and a further group of capacitors, a plurality of switches, and a plurality of branches that include the plurality of switches and the group of capacitors;
- wherein the plurality of multipliers are configured to:
- receive, by the plurality of switches, the digital signals from the memory array;
- execute multibit computation operations with the plurality of capacitors and the plurality of switches forming a C-2C ladder based on the digital signals by controlling the plurality of switches using the digital signals to electrically connect or disconnect an input analog signal to the group of capacitors;
- and
- generate an output analog signal based on the multibit computation operations.
8 more elements
A method comprising:
- receiving, with a plurality of switches of a plurality of multipliers of a multiply-accumulator (MAC), digital signals corresponding to bits of a multibit value from a memory array, wherein the plurality of multipliers include a plurality of capacitors including a group of capacitors and a further group of capacitors, the plurality of switches, and a plurality of branches that include the plurality of switches and the group of capacitors;
- executing, with the plurality of capacitors and the plurality of switches forming a C-2C ladder, multibit computation operations based on the digital signals by controlling the plurality of switches using the digital signals to electrically connect or disconnect an input analog signal to the group of capacitors;
- and
- generating, with the plurality of multipliers, an output analog signal based on the multibit computation operations.
1 more element
Dependencies are inferred from the claim text.